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65816 C64 With Discrete Instead of PAL

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digidice

Post subject:

Posted: Mon Oct 11, 2010 7:12 pm

Joined: Sun Oct 03, 2010 7:45 am
Posts: 43

@BigDumbDinosaur

Okay, well a couple of comments, the series of logic will be the fastest IC i can lay my hands on, ie, there is a 74F138 but no 74ABT138. so wherever the the fastest part i can find will be the one used. My library doesnt have all the 74 series so I am using what performs the same function.

#1 Unused Inputs will be pulled high, Hadn't got to that yet

#3 Gate on IC12 is hooked to the VDA now
#4 Here again the Vector pin must be inverted in order to disable the SRAM during startup.
#5 A AND gate from /Ø2 and RWB to the /WE on the SRAM? That should qualify?
#6 You say Potato, I say Potàto.

I can put GND signals in there it it makes it easier for everyone.

Changed the EEPROM to a 32K and mapped it to after the first 32K in system memory ($8000)

Lots more stuff to pick over today's schematic, Version 5 added Chris Wards IDE interface schematic into the design, have not mapped it to a memory location yet...

Big question is should I use the 65c22 for the PS/2 interface or should I use a PIC to do the decoding? (other thoughts, USB, VGA video, Ethernet would be nice too ) Should move this whole topic to "off the cuff 816"

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GARTHWILSON

Post subject:

Posted: Mon Oct 11, 2010 7:55 pm

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8432
Location: Southern California

Quote:

I put a 64K eeprom in 0 to 65535 (FFFF) then whats the memory going to do because I have 4 4Meg static ram chips. use an inverted VDP on the 138?

If you have ROM in the first 64K of address space what do you plan to do about zero page and a stack? At reset, the '816 sets the stack pointer to $01FF and the direct (zero) page pointer to $0000. You can't move the stack until the '816 is in native mode, and even then, both the stack and page zero must remain in the lowest 64K address range. Not going to be possible if ROM is in that area.

I noticed that last night too, but thought I better cool it after making my other mistakes and take another look after some rest. If you want to ever run in 6502-emulation mode (I personally don't have any reason to), then you can put it in native mode immediately when you start the reset routine, so to make my address decoding simpler for my next workbench computer, the tentative plan is to put I/O in the first couple of K of the address map. One thing that does bring to mind however is that even at reset, the processor does immediately write to the stack in page 1 (since it comes up in emulation mode), before even the first instruction of the reset routine is fetched, so I need to see if that might require that I immediately fix something in the I/O setup, before even getting out of the reset routine.

But yes, direct page and the hardware stack have to be in bank 0. There's really no reason to have 64K of ROM in a computer like this. That is way more than you will need unless you want large, permanent data tables or files, and those don't need to be in bank 0. For very full-featured high-level languages or editor, you would probably want to be able to make updates more easily than you can if they're in ROM.

Quote:

What's the purpose of IC5?

Never mind. Evidently I hadn't gulped enough coffee when I was looking at the schematic.

You too, huh? Now I don't feel lonely.

On the unconnected inputs, I figured he just hadn't completed all the details yet and he was going to get to it; but those do seem almost too trivial to not take care of right away.

Quote:

My library doesnt have all the 74 series so I am using what performs the same function.

You can make your own parts, can't you??

digidice, it's great that you're diving into this head first, but I'm thinking it might not be a bad idea for you to make your first computer simpler. Our first efforts tend to be overblown which makes them hard to complete at all, either because we bit off more than we could chew, or after it's built we find it has problems we don't yet have the knowledge to fix or problems that can't be fixed without starting over on part of it. My first one worked, but I didn't have the experience yet to know what would be useful, and this one was not much good for anything. My next one was a lot less work and did a lot more.

_________________
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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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digidice

Post subject:

Posted: Mon Oct 11, 2010 10:21 pm

Joined: Sun Oct 03, 2010 7:45 am
Posts: 43

GARTHWILSON wrote:

Quote:

My library doesnt have all the 74 series so I am using what performs the same function.

Yes, I can make my own parts, I did make quite a few while I was using expresssch, but I started using Eagle and have not messed with the libraries.

I actually spent a lot of time with the APATCO 6502 computer trainer kit and messed around quite a bit on the ELF2K (1802 RCA CPU) Plus what I remember from 20 plus years ago with the C64 hardware. I can understand the whole biting off more than you can chew, but I really like the idea of 16M of memory address space and 16 bit capability of the 816 (I wish there was a 32bit 6502).

So, yes the design is getting more complicated, with the hope that when its all said and done It will be a nice expandable system, As I may have mentioned before I have thought about using a PC ISA back plane which would support expanded devices, even if its not PC ISA compatible, Maybe even an S100 Bus.

Here are the goals Im looking at,
Useful.
Low Cost to performance.
Fully populated memory.
Expandable. (VGA, Sound, USB, IDE, Serial/Parallel, Ethernet, etc.)
Easy to assemble. (IE no BGA or something that is difficult to solder up.)

I know most of you good people have been down the road before, And because I want more than just an LCD display a Ram and Rom IC the design is getting much more complicated. Hence I am asking for input on where I might be going wrong. I really would like to keep this an open project where everyone could build one and maybe it might take on a life of its own? especially if its expandable.

EDIT: I changed the EEPROM to and 32K maybe I should make it a 16K or maybe 8K? Im not sure how much I will need to code up a decent BIOS.

Your thoughts?

Kent

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GARTHWILSON

Post subject:

Posted: Mon Oct 11, 2010 11:05 pm

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8432
Location: Southern California

Quote:

(I wish there was a 32bit 6502)

We had a long discussion about this at viewtopic.php?t=1419 where I presented the idea of a 32-bit 6502 in hopes of attracting the programmable-logic designers, something I did not succeed in. With a 32-bit data bus as well, basically everything is in "zero page" (although you can move its starting point around for various tasks in multitasking) and there are no banks. I had to explain myself several times as to why there's no need for 8- and 16-bit operations just as the 6502 has no 4-bit operations. I am very much opposed to giving it a Harvard architecture though. That would definitely wipe out some of the 6502's benefits and keep it from being a 65-anything.

As for having fully a populated memory: The dollar cost of doing that in 5V SRAM is pretty high. Obviously it will still be worth it to some users. 16 megabytes of 10ns SRAM is about $300 just in RAM chips, but I don't know if there's any point in getting such fast ones if the heavy capacitive bus load of 32 SRAMs promises to slow things down substantially. DRAM is much cheaper but more complicated to operate, and it's slower, meaning that then you will probably need a cache system too.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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digidice

Post subject:

Posted: Mon Oct 11, 2010 11:29 pm

Joined: Sun Oct 03, 2010 7:45 am
Posts: 43

GARTHWILSON wrote:

Quote:

(I wish there was a 32bit 6502)

We had a long discussion about this at viewtopic.php?t=1419 where I presented the idea of a 32-bit 6502 in hopes of attracting the programmable-logic designers, something I did not succeed in. With a 32-bit data bus as well, basically everything is in "zero page" (although you can move its starting point around for various tasks in multitasking) and there are no banks. I had to explain myself several times as to why there's no need for 8- and 16-bit operations just as the 6502 has no 4-bit operations. I am very much opposed to giving it a Harvard architecture though. That would definitely wipe out some of the 6502's benefits and keep it from being a 65-anything.

As for having fully a populated memory: The dollar cost of doing that in 5V SRAM is pretty high. Obviously it will still be worth it to some users. 16 megabytes of 10ns SRAM is about $300 just in RAM chips, but I don't know if there's any point in getting such fast ones if the heavy capacitive bus load of 32 SRAMs promises to slow things down substancially. DRAM is much cheaper but more complicated to operate, and it's slower, meaning that then you will probably need a cache system too.

Without being to ostensive, Maybe it is time that we look hard at a VHDL design of your 6532 idea, I think it would be something that could pay off in spades. I read your wish list and I thought it was a really good. I cant see anything that a person would want to change, It really would not have to be backwards compatible, a cross compiler could take 02 code and make it operate on the 32 IMHO. Backwards compatibility has been the bane of x86 tech for nearly 20 years now.

What about your ram chips???

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GARTHWILSON

Post subject:

Posted: Tue Oct 12, 2010 12:07 am

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8432
Location: Southern California

Quote:

What about your ram chips???

It's a module, like the memory modules in PCs that are a small PC board with a bunch of RAM ICs on them and a few chip capacitors.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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digidice

Post subject:

Posted: Tue Oct 12, 2010 12:10 am

Joined: Sun Oct 03, 2010 7:45 am
Posts: 43

GARTHWILSON wrote:

Quote:

What about your ram chips???

It's a module, like the memory modules in PCs that are a small PC board with a bunch of RAM ICs on them and a few chip capacitors.

Okay, details man! Details!
NS access times? Cost?

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GARTHWILSON

Post subject:

Posted: Tue Oct 12, 2010 1:23 am

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8432
Location: Southern California

Quote:

Okay, details man! Details!
NS access times? Cost?

I'm in the process of designing it. The initial one is planned for holding 8 512Kx8 10ns SRAMs, which currently are at a little under $10 per chip [but see the edit below], and I probably won't initially be able to buy enough at a time to get any significant discount. So my cost on just the chips will probably be around $70 per set of 8. I haven't figured out yet how the tool-up cost of boards will amortize out. The cost for each bare PC board is rather trivial, but the PCB manufacturing set-up charges are not, so the quantity will dramatically affect the per-piece price. Then I'll have to factor in the assembly labor. The other parts' cost is piddly. I've done enough investigating to know that it's feasible, but it will be awhile before I can sharpen my pencil and come up with a final price. After this first one, I hope to make other densities of SRAM modules and other types of modules.

Edit: I came across this again five years later, and realized I never edited it to give the info. The module is shown on the front page of my website (linked at the bottom of this post), and the data sheet is at http://wilsonminesco.com/WM-1_4Mx8SRAMmodule4-23-20.pdf . I wrote above that the ICs were nearly $10 each. I'm getting them now, in quantity, at $2.50/each, probably far less than you can get them in small quantities, then there's the PCB itself, connector, and capacitors, and I am letting the parts go for my cost and adding about $40 for my labor (if the module is fully populated) to assemble and test each module. The price on the ICs is different every time I order though. (Hopefully now it will only go down, but that has not always been the case.) As of Jan 2017, I'm asking $69 for each fully populated module. Lesser populated ones (ie, having less than 8 SRAM ICs on it) cost somewhat less. [end_edit]

A discussion of the consortium plan is material for another forum topic, but here's a taste. Daryl is in on this informal "consortium" too, and others are welcome. The idea of the consortium is to have various members who, although not obligated to each other in any way (eg, they are not business partners together nor are they bound by contract) agree on simple technical standards (like 65SIB) for the benefit of all, and cooperate to offer different compatible modules and other hardware, to make 6502 construction and use easier and more rewarding for hobbyists and possibly schools and anyone else interested. I've been wanting to do this for years, but now my job situation makes me think I should get something going on the side, which is an added excuse and motivation.

There was a cartoon published over 100 years ago. Two neighbors are talking, and one says to the other, "I hear you've gotten yourself an automobile. Why haven't I seen you out in it?" and the other, both proud and embarrassed, says, "Oh, I'm still learning to make my own repairs." With no history of automobiles to go on yet, the buyer who received his prize possession in a crate "with some assembly required" had to figure out how to get it going (with no support) and then how to do the regularly required repairs, or it was of no use to him. That's kind of how the 6502 hobby world has been. If the consortium goes as I imagine it, the 6502 world should be gaining a lot of momentum.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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digidice

Post subject:

Posted: Tue Oct 12, 2010 5:45 am

Joined: Sun Oct 03, 2010 7:45 am
Posts: 43

The consortium sounds like a good idea, the premise of making modular components that hook together like an erector set would be really nice, Is there any docs about how the hardware parts should be connected for a standard?

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GARTHWILSON

Post subject:

Posted: Tue Oct 12, 2010 8:08 am

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8432
Location: Southern California

Quote:

Is there any docs about how the hardware parts should be connected for a standard?

Since the consortium has just started to form, there's nothing to offer yet except that before the consortium idea was born, we developed the 65SIB spec here on the forum.

One other very simple specification I anticipate will be presenting and finalizing soon is a hobbyist-friendly I²C connection standard for sharing tiny I²C hot-pluggable plug-in modules. [Edit: It's at viewtopic.php?f=4&t=2155 .] We're definitely not trying to hide anything but just have been too busy to bring it up for comment. It's basically the same as I've used for the half-postage-stamp-sized serial EEPROM modules I've posted pictures of but there's an additional pin for IRQ\ (like for real-time-clock alarm output) and a keyed connector to keep one from plugging it in backwards. I would be very surprised if there's any disagreement to iron out, because it's just so simple. There was a little company in, IIRC, Australia that tried to establish a standard connector for I²C modules; but theirs was not commonly available, nor did it fit into standard perfboard we hobbyists use with ten holes per inch. [Edit: Now we also have the hobbyist-friendly SPI-10 connector standard for tiny SPI flash and other modules.]

I believe another member is devising a low-pin-count (maybe 16?) parallel expansion bus for custom I/O peripherals like making your own video card, implemented using low-cost microcontrollers but which appear to hang directly off the CPU bus even though they don't load it significantly or slow it down like other buses do. Four-phase transfers allow peripherals to run at their own maximum speed without the computer having to know what that is. The low pin count makes construction easier, and the ATmega or PIC microcontrollers are quite a bit cheaper than CPLDs and easier to program at home. They should be made available pre-programmed for those who aren't into programming their own. This is not a competitor to 65SIB. They meet different needs.

Then of course will be actual hardware we hope to make available. Your "erector set" analogy kind of gives the idea, and Wally Daniels has used the term "Legos," but it would be nice to find a term that relates more to the fact that 's more specific to the completed modules made available.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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kc5tja

Post subject:

Posted: Tue Oct 12, 2010 4:28 pm

Joined: Sat Jan 04, 2003 10:03 pm
Posts: 1706

GARTHWILSON wrote:

I presented the idea of a 32-bit 6502 in hopes of attracting the programmable-logic designers, something I did not succeed in.

I'd like to try my hand at Verilog after the end of this year. I think I will tackle this design. Contact me again if I forget, please.

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kc5tja

Post subject:

Posted: Tue Oct 12, 2010 4:33 pm

Joined: Sat Jan 04, 2003 10:03 pm
Posts: 1706

digidice wrote:

Backwards compatibility has been the bane of x86 tech for nearly 20 years now.

It's also what ensured its market success.

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digidice

Post subject:

Posted: Tue Oct 12, 2010 5:50 pm

Joined: Sun Oct 03, 2010 7:45 am
Posts: 43

kc5tja wrote:

digidice wrote:

Backwards compatibility has been the bane of x86 tech for nearly 20 years now.

It's also what ensured its market success.

Thats not exactly true, It may have been part of the factor, but overall machine expense was the number one reason, You could buy 3 or 4 PC's for the price of a Mac.

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BigEd

Post subject:

Posted: Tue Oct 12, 2010 5:57 pm

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10800
Location: England

GARTHWILSON wrote:

...One thing that does bring to mind however is that even at reset, the processor does immediately write to the stack in page 1 (since it comes up in emulation mode), before even the first instruction of the reset routine is fetched...

Hi Garth
are you sure about this? It looks like the nMOS 6502 doesn't do this - indeed it seems like a bad idea because reset writing to the stack is a destructive thing to do. (Even if reset was used as a warm reset, one wouldn't normally worry about preserving the stack content, but even so... maybe page 1 has something important mapped in, even peripherals, or the famous 128 bytes mapped into both pages 0 and 1.)

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GARTHWILSON

Post subject:

Posted: Tue Oct 12, 2010 6:36 pm

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8432
Location: Southern California

Ed, I haven't tried it on an NMOS one, but I have with CMOS, single-cycling and seeing what's on the buses at each phase-2-high time. This was before I saw the same info in the cycle-by-cycle info in WDC's data sheet. It does indeed push the address and status on the stack, which might be a good thing if you wanted to see which way the bear went into the woods that required the reset to get control back. I've never done that though. RST is basically an interrupt, although I never thought of using it that way. Hmmm... maybe there's another hidden use there.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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