well .. in fact I'm new in here .
Few years ago I have made project with atmega128 and some adc chip . here is some videos i have made today . http://www.youtube.com/watch?v=Z-woMgq0BAE
What you see is a finger touch on the digital side . ( That project was newer done after i have bay digital oscilloscope) .
So in this project atmega128 (at 16mhz) was sharing memory with cpld , to display data's on vga display (640x480) .
no problems at all . My point is ... 6502 or even 65816 are disaster to deal with , the timings are so difficult to understand . At the moment I have the same problem what mr. Deryl has ,on my old board ( with hct245 on data side ) my cpu was working fine with 1, 2, 4 8 mhz , after I rebuild it .. cpu is working only ( ONLY) at 16 mhz (negative clock of vga clock) . So finally is any of you has some experience with sharing memory between cpu (65816) and vga ??? in vhdl ?
Greetings
New to 6502 - 65816 SBC projects
New to 6502 - 65816 SBC projects
Last edited by bound on Wed Sep 22, 2010 11:32 pm, edited 1 time in total.
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GARTHWILSON
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Microcontrollers, whether Atmega, PIC, or whatever, are pretty much self-contained and as such have virtually no timing requirements. So that part is easy. A nice thing about the 6502 as a microprocessor however is the very simple bus structure. For an aircraft product I designed in 1993, when the microcontroller selection on the market was much more limited and we needed a lot of ROM plus EEPROM, the microcontroller we settled on turned out to be too difficult to get, so I made a little board with a 6502. It was so easy I didn't have to look up any timings, I didn't breadboard it, and I didn't even draw up a schematic until after that board was laid out and in production. We sold it for 15 years and never had any trouble with it.
If I can add something here, I think "simplicity" has multiple meanings. The 6502/65816's bus is very simple, and closely resembles many high-performance buses found in ASICs and programmable logic. Compare Wishbone against 65xx bus, and you'll notice an immediate resemblance.
But, I can feel for Bound's reaction too, because there is a certain kind of simplicity that having a "stateful" bus (like Multibus) affords too. You can use slower parts, not have to worry so much about which clock phase something needs to be valid, etc. The cost, of course, is performance. Multibus takes three to four cycles to transfer one unit of data, while the 65816 takes one cycle.
With that being said, my experience with the 65816 has been negative only when dealing with a clock with a slew greater than 5ns. Most of the chip's timings are pretty lax (except for ABORT#, I think everything is sampled on the falling edge of phase-2 now-a-days), but when WDC says the 65816 must have a 5ns or better slew on the phase-2 (or phase-0) input, they really mean it.
Another tip to working with the 65xx line is that the clock signal is not edge sensitive. It is, in fact, level-sensitive. Hence, most of your external logic, if not integrated through some other means, will also need to use level-sensitive logic. This is why WDC recommends transparent latches instead of edge-triggered devices for capturing the bank address byte on the 65816, for example.
But, I can feel for Bound's reaction too, because there is a certain kind of simplicity that having a "stateful" bus (like Multibus) affords too. You can use slower parts, not have to worry so much about which clock phase something needs to be valid, etc. The cost, of course, is performance. Multibus takes three to four cycles to transfer one unit of data, while the 65816 takes one cycle.
With that being said, my experience with the 65816 has been negative only when dealing with a clock with a slew greater than 5ns. Most of the chip's timings are pretty lax (except for ABORT#, I think everything is sampled on the falling edge of phase-2 now-a-days), but when WDC says the 65816 must have a 5ns or better slew on the phase-2 (or phase-0) input, they really mean it.
Another tip to working with the 65xx line is that the clock signal is not edge sensitive. It is, in fact, level-sensitive. Hence, most of your external logic, if not integrated through some other means, will also need to use level-sensitive logic. This is why WDC recommends transparent latches instead of edge-triggered devices for capturing the bank address byte on the 65816, for example.
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ElEctric_EyE
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kc5tja wrote:
...Another tip to working with the 65xx line is that the clock signal is not edge sensitive. It is, in fact, level-sensitive. Hence, most of your external logic, if not integrated through some other means, will also need to use level-sensitive logic. This is why WDC recommends transparent latches instead of edge-triggered devices for capturing the bank address byte on the 65816, for example.
Another concern for a designer is use of Phase 2 In? to control all other peripherals, or Phase 2 Out? We are all used to use Phase 2 Out from the CPU. The WDC datasheet concerning the 6502 says otherwise...
Yes , the 245 and 573 logic plus lvt08 or vhc08 (to format irq, mnib ,clock signals ) and one hct00 for rd wr signal is required . That will make you system stable . If you designing system with mixed voltage ... remember to provide clear signals for you cpu . end of story .
PS . fpga suck ! If you wont to be sure about you timing design go for cpld's
PS . fpga suck ! If you wont to be sure about you timing design go for cpld's