dromaius816 - a new 65816 emulator

Topics pertaining to the emulation or simulation of the 65xx microprocessors and their peripheral chips.
daniMolina
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dromaius816 - a new 65816 emulator

Post by daniMolina »

Short story: I have just started working on a half-cycle exact 65816 emulator.

Long story: New year, new project—it seems I did it again.

This is my first post in the Emulation board. In fact, this is my first attempt at emulation. So, once again, the beginning of a long journey, it seems. Some of you may know me from my main project, 74HCT6526, a discrete implementation of the MOS6526. That project is currently on a longer-than-expected break (14 months now, with at least 6 more to go) as my new house (and with it, my new lab) is still under construction.

To keep my mind busy during this time, I started working on a computer based on the 65816. I needed a new challenge, and having no experience with this CPU, it seemed like the perfect choice.

And that brings us to today. With no experience and no lab, I thought having an emulator for my computer would be useful. I’ve seen several people build emulators for their own projects, and given my current situation, a project that requires nothing more than a laptop and coffee is exactly what I need.

After some research, I came across this 6502 emulator called Dromaius. It’s quite low-level and capable of emulating a Commodore PET. I could have looked for an existing 65816 emulator, but if I manage to adapt this project and create a 65816 version, I will gain an incredible amount of knowledge about the CPU.

So far, I’ve managed to extract the core from the original project and create a basic barebones version of my own. I’ve more or less figured out how it works, and it seems quite clever to me.

The core of the emulator is built around chips, signals, and devices. Chips represent, well, chips. Each has a list of pins, some of which trigger an emulation "process," and each has a scheduled next operation time. Take the clock source, for example—it has only an output pin, and when it "ticks," a new process is scheduled for half a cycle later. There’s a thread continuously running that checks all chips' scheduled processes, so when one is due, the chip’s outputs are recalculated.

The 6502 is implemented as a special type of chip called, unsurprisingly, "cpu." Each change on its clock input triggers a process, and to model certain CPU delays (such as the time until the address is valid), its next process is scheduled for the exact delay after the corresponding clock edge.

Signals represent connections between chips. A device is a collection of chips and signals, making it, effectively, an emulated computer. When created, the device spawns a new thread that runs the emulation in an infinite loop. It’s not the fastest emulator ever—it can emulate a PET at about 600–700 kHz on my (three-year-old Ryzen 7) computer.
early_pet.gif
My project is not yet public on GitHub. It’s only four days old, and right now, it's a mess. It will be public soon enough, as I'm currently cleaning up the code before making an even bigger mess.

As usual, I’m starting this thread to share my progress—and to remind myself that I have work to do.

Cheers!
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BigEd
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Re: dromaius816 - a new 65816 emulator

Post by BigEd »

Sounds good to me! Starting from a working emulator (in C, and open source) seems like a very good place to start. Look forward to your updates.
daniMolina
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Re: dromaius816 - a new 65816 emulator

Post by daniMolina »

If I want to start moving... taking the first steps is mandatory.

So, after some tidy up, repository is now public at https://github.com/dmolinagarcia/dromaius816.

Let´s see what is my target. This is what dromaius looks like :
VirtualBox_Dromaius_07_02_2025_15_14_38.png
A full (a think) PET2001. 6520, 6522, memory, video, tape, disk, everything is emulated. You can peek into the support chips' registers, into the CPU. It also has a built-in logic analyzer. Quite an amazing setup!

As my final goal is to emulate my Nova 64, I will need to implement additional chips. I am planning to even emulate an SD Card so I can test my read/write functions. The functionality I plan to build into my main FPGA (To handle devices, keyboard, storage, mouse, DRAM) will also be recreated. The ultimate goal is to learn and understand what am I doing, so when the time comes to build real hardware, it can be less painful.

The current status of Dromaius816 is simpler.... much much simpler.
VirtualBox_Dromaius_07_02_2025_15_22_49.png
Everything has been ripped off, except for clock, reset, and CPU. It is helping me to understand how the emulator works, before creating more complicated stuff.

My TO-DO for the weekend, keep on studing the emulator core, and how the clock generator and reset generator work. As this two components don't have a panel to check their state (Not to much to check anyway) I will create them, to gain some kwowledge on the GUI itself.

As a side note, I think the last thing I coded using C, was a checkers game back in college, around 25 years ago. :)
daniMolina
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Re: dromaius816 - a new 65816 emulator

Post by daniMolina »

Hi all!

Although I still haven't started working on the 65816 emulation itself, there's been quite some progress during this last days. My kwowledge on the original emulator has been expanding everyday, and I am adding one functionality at a time to mine.

My latest addition, is the logic analyzer, which I consider quite important for my goals. In the original emulator it was only available for the Commodore Pet emulation, and other smaller systems built into the emulator didn't have that. I've managed to understand how the Logic Analyzer captures and represents data and adapted it to my own emulated computer.

One thing that was missing from the original, was the ability to plot buses as a single line. Before, each bus line was an independent signal, making them quite impossible to read.
logic_analyzer_with_no_buses.png
I have modified the LA so, if it detects a whole bus is added (DB0:7 or AB0:15), it colapses into a single line, much as any LA software would do
logic_analyzer_with_buses.png
logic_analyzer_with_buses.png (8.07 KiB) Viewed 5397 times
As I said, no advances in 65816 emulation yet, but I am so happy with this feature, that I wanted to share it with the forum.

I still have some ideas to improve the LA. It has a very limited range of zoom options, and it doesn't allow scrolling. I am not going to get bored, that's for sure :)

Cheers!

Ninja edit: Fully adjustable zoom has been added :)
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Re: dromaius816 - a new 65816 emulator

Post by daniMolina »

Progress!!!

One by one, all the features from the original emulator are being built into mine. Today, I managed to implement a 64KB ram into the emulation.

It may not be a huge step. After all, it is something already done, but I don't mark a feature as "Added", unless I understand how it works. Proof of this, is that I have extended the RAM form 32KB to 64KB. I had to remove some components, such as a IO chip (6520) and a 32KB ROM, and "rewire" the RAM. The original 6502 cpu seems happy about it, and runs code from it as expected.

Meanwhile, I have remove all decoding logic from my emulated 65816 CPU, so any opcode is processed as a NOP. I am working on the internal registers right now. Adding registers is trivial, extending current one is trivial too. Adding more flags to build the status register is also done. Both the emulator and the GUI are quite happy about it :)

My current focus is on different areas at the moment.
- Emulation flag is created and I can manipulate it in the code. It is set during the reset sequence. I want to implement SEC,CLC and XCE instructions first. When E changes, the status register should reflect the current CPU mode.
- Manipulation of M and X flags will follow. I am still learning how the CPU works. I know these two flags control the with of the accumulator and the index registers, but, honestly, I don't even know which instructions modify them. I could've looked it up while I was writing this but... I really want everybody to know where I am standing right now!
- Output of BA when needed. I could make it so BA is present on the bus during PHI low with minor changes to the emulator core. This will completely ignore some timings, but the goal is not to be absolutely exact with the timing. This is emulation, not simulation so... could it be good enough?

I'm attaching a capture of the startup and the first few cycles of the NOP free run. I just love the Logic Analyzer!

Cheers!
Attachments
nop_free_run.png
nop_free_run.png (10.91 KiB) Viewed 5250 times
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BigEd
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Re: dromaius816 - a new 65816 emulator

Post by BigEd »

Splendid - I do like a logic analyser view.

If you haven't already found it, Bruce's document on the '816 details all known behaviours and quirks, I think.
http://6502.org/tutorials/65c816opcodes.html
daniMolina
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Re: dromaius816 - a new 65816 emulator

Post by daniMolina »

BigEd wrote:
Splendid - I do like a logic analyser view.

If you haven't already found it, Bruce's document on the '816 details all known behaviours and quirks, I think.
http://6502.org/tutorials/65c816opcodes.html
Yep, I've got that one. It is an splendid document! I have quite a long list of documents to read...

The 6502 original hardware and programing manuals. Although I don't think I need to read these, they are helping me understand some parts of the original emulator. I have been programming for the 6502 for some time already (as a hobbyist, nothing professional) but there are some inner quirks that are complete unknowns for me.
The WDC65c816 Datasheet, of course.
The 65816 programming manual.
And a ton of small articles, blog posts, forum posts...
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Re: dromaius816 - a new 65816 emulator

Post by daniMolina »

Two little achievements to add to the list.

A proper fetch/decode loop is now implemented into the emulation. On decode cycle 0, the opcode is fetched into the IR. From there on, a function is called using a function array based on the opcode. Each opcode function advances the decode cycle counter until the instruction is executed, returning the decode cycle to 0.

Only NOP is executed at the moment, so, not too much more than yesterday but now I can focus on implementing opcodes.

Here you can see a log of the CPU starting up, going through the 7 cycle reset sequence, fetching the reset vector, and executing a couple fof NOPS

Code: Select all

[ 2025-02-24 13:20:22.364 ] - CYCLE_END         Decode_cycle: -1 IR: 0
[ 2025-02-24 13:20:22.364 ] - CYCLE_BEGIN ----  Decode_cycle: 0 IR: 0
[ 2025-02-24 13:20:22.364 ] - Address bus: 0000
[ 2025-02-24 13:20:22.535 ] - CYCLE_MIDDLE      Decode_cycle: 0 IR: 0
[ 2025-02-24 13:20:22.685 ] - CYCLE_END         Decode_cycle: 0 IR: 0
[ 2025-02-24 13:20:22.685 ] - CYCLE_BEGIN ----  Decode_cycle: 1 IR: 0
[ 2025-02-24 13:20:22.846 ] - CYCLE_MIDDLE      Decode_cycle: 1 IR: 0
[ 2025-02-24 13:20:23.016 ] - CYCLE_END         Decode_cycle: 1 IR: 0
[ 2025-02-24 13:20:23.016 ] - CYCLE_BEGIN ----  Decode_cycle: 2 IR: 0
[ 2025-02-24 13:20:23.016 ] - Address bus: 0100
[ 2025-02-24 13:20:23.194 ] - CYCLE_MIDDLE      Decode_cycle: 2 IR: 0
[ 2025-02-24 13:20:23.384 ] - CYCLE_END         Decode_cycle: 2 IR: 0
[ 2025-02-24 13:20:23.384 ] - CYCLE_BEGIN ----  Decode_cycle: 3 IR: 0
[ 2025-02-24 13:20:23.384 ] - Address bus: 01ff
[ 2025-02-24 13:20:24.003 ] - CYCLE_MIDDLE      Decode_cycle: 3 IR: 0
[ 2025-02-24 13:20:24.197 ] - CYCLE_END         Decode_cycle: 3 IR: 0
[ 2025-02-24 13:20:24.197 ] - CYCLE_BEGIN ----  Decode_cycle: 4 IR: 0
[ 2025-02-24 13:20:24.197 ] - Address bus: 01fe
[ 2025-02-24 13:20:24.409 ] - CYCLE_MIDDLE      Decode_cycle: 4 IR: 0
[ 2025-02-24 13:20:24.598 ] - CYCLE_END         Decode_cycle: 4 IR: 0
[ 2025-02-24 13:20:24.598 ] - CYCLE_BEGIN ----  Decode_cycle: 5 IR: 0
[ 2025-02-24 13:20:24.598 ] - Address bus: fffc
[ 2025-02-24 13:20:24.759 ] - CYCLE_MIDDLE      Decode_cycle: 5 IR: 0
[ 2025-02-24 13:20:24.928 ] - CYCLE_END         Decode_cycle: 5 IR: 0
[ 2025-02-24 13:20:24.928 ] - CYCLE_BEGIN ----  Decode_cycle: 6 IR: 0
[ 2025-02-24 13:20:24.928 ] - Address bus: fffd
[ 2025-02-24 13:20:25.103 ] - CYCLE_MIDDLE      Decode_cycle: 6 IR: 0
[ 2025-02-24 13:20:25.293 ] - CYCLE_END         Decode_cycle: 6 IR: 0
[ 2025-02-24 13:20:25.293 ] - CYCLE_BEGIN ----  Decode_cycle: 0 IR: 0
[ 2025-02-24 13:20:25.293 ] - Fetching into IR
[ 2025-02-24 13:20:25.293 ] - Fetching eaea
[ 2025-02-24 13:20:25.478 ] - CYCLE_MIDDLE      Decode_cycle: 0 IR: 0
[ 2025-02-24 13:20:25.478 ] - Fetching into IR
[ 2025-02-24 13:20:25.680 ] - CYCLE_END         Decode_cycle: 0 IR: 0
[ 2025-02-24 13:20:25.680 ] - Fetching into IR
[ 2025-02-24 13:20:25.680 ] - Fetched: ea
[ 2025-02-24 13:20:25.680 ] - CYCLE_BEGIN ----  Decode_cycle: 1 IR: ea
[ 2025-02-24 13:20:25.680 ] - Address bus: eaeb
[ 2025-02-24 13:20:25.861 ] - CYCLE_MIDDLE      Decode_cycle: 1 IR: ea
[ 2025-02-24 13:20:26.950 ] - CYCLE_END         Decode_cycle: 1 IR: ea
[ 2025-02-24 13:20:26.950 ] - NOP Opcode ea executed
[ 2025-02-24 13:20:26.950 ] - CYCLE_BEGIN ----  Decode_cycle: 0 IR: ea
[ 2025-02-24 13:20:26.950 ] - Fetching into IR
[ 2025-02-24 13:20:26.950 ] - Fetching eaeb
[ 2025-02-24 13:20:28.270 ] - CYCLE_MIDDLE      Decode_cycle: 0 IR: ea
[ 2025-02-24 13:20:28.270 ] - Fetching into IR
[ 2025-02-24 13:20:29.196 ] - CYCLE_END         Decode_cycle: 0 IR: ea
[ 2025-02-24 13:20:29.196 ] - Fetching into IR
[ 2025-02-24 13:20:29.196 ] - Fetched: ea
[ 2025-02-24 13:20:29.196 ] - CYCLE_BEGIN ----  Decode_cycle: 1 IR: ea
[ 2025-02-24 13:20:29.196 ] - Address bus: eaec
[ 2025-02-24 13:20:54.275 ] - CYCLE_MIDDLE      Decode_cycle: 1 IR: ea
[ 2025-02-24 13:20:54.429 ] - CYCLE_END         Decode_cycle: 1 IR: ea
[ 2025-02-24 13:20:54.429 ] - NOP Opcode ea executed
[ 2025-02-24 13:20:54.429 ] - CYCLE_BEGIN ----  Decode_cycle: 0 IR: ea
[ 2025-02-24 13:20:54.430 ] - Fetching into IR
[ 2025-02-24 13:20:54.430 ] - Fetching eaec
[ 2025-02-24 13:20:54.609 ] - CYCLE_MIDDLE      Decode_cycle: 0 IR: ea
[ 2025-02-24 13:20:54.609 ] - Fetching into IR
[ 2025-02-24 13:20:54.764 ] - CYCLE_END         Decode_cycle: 0 IR: ea
[ 2025-02-24 13:20:54.764 ] - Fetching into IR
[ 2025-02-24 13:20:54.764 ] - Fetched: ea
[ 2025-02-24 13:20:54.764 ] - CYCLE_BEGIN ----  Decode_cycle: 1 IR: ea
[ 2025-02-24 13:20:54.764 ] - Address bus: eaed
[ 2025-02-24 13:20:54.926 ] - CYCLE_MIDDLE      Decode_cycle: 1 IR: ea
[ 2025-02-24 13:20:55.075 ] - CYCLE_END         Decode_cycle: 1 IR: ea
[ 2025-02-24 13:20:55.075 ] - NOP Opcode ea executed
[ 2025-02-24 13:20:55.075 ] - CYCLE_BEGIN ----  Decode_cycle: 0 IR: ea
[ 2025-02-24 13:20:55.075 ] - Fetching into IR
[ 2025-02-24 13:20:55.075 ] - Fetching eaed
Also, the BankAdress is now present on the data bus during PHI2 LOW. Not timing perfect, but on each clock transition (I think) I have the right value on the bus, and this should be good enough for my emulation.
bankaddress.png
bankaddress.png (8.24 KiB) Viewed 5112 times
I don't have the PBR or DBR implemented yet so, I am writing a harcoded 0xFE when I am fetching the opcode, and 0xFF when executing.

Next milestone, decoding and implementing all instructions related to mode switching (Native vs Emulation, 8 vs 16 bit registers)

Edit: Mode switching refers only to the change between Native and Emulation. Changing registers width is not a mode change. (Thanks BDD for pointing that out)
Last edited by daniMolina on Mon Feb 24, 2025 7:58 pm, edited 1 time in total.
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BigDumbDinosaur
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Re: dromaius816 - a new 65816 emulator

Post by BigDumbDinosaur »

daniMolina wrote:
Next milestone, decoding and implementing all instructions related to mode switching (Native vs Emulation, 8 vs 16 bit registers)

The 816 has two operating modes: emulation and native.  Changing register width whilst operating in native mode isn’t “mode switching,” as instruction behavior in itself is unaffected by register size changes.

It should be noted that in native mode, internal operations are carried out 16 bits at a time, regardless of register widths.  This characteristic explains, among other things, why branching across a page boundary in native mode doesn’t use an extra clock cycle, and why instructions such as INC A and DEX take two cycles regardless of register width.
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daniMolina
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Re: dromaius816 - a new 65816 emulator

Post by daniMolina »

BigDumbDinosaur wrote:
daniMolina wrote:
Next milestone, decoding and implementing all instructions related to mode switching (Native vs Emulation, 8 vs 16 bit registers)

The 816 has two operating modes: emulation and native.  Changing register width whilst operating in native mode isn’t “mode switching,” as instruction behavior in itself is unaffected by register size changes.

It should be noted that in native mode, internal operations are carried out 16 bits at a time, regardless of register widths.  This characteristic explains, among other things, why branching across a page boundary in native mode doesn’t use an extra clock cycle, and why instructions such as INC A and DEX take two cycles regardless of register width.
You are absolutely right; thanks for pointing that out. As you might have guessed, I am a complete beginner when it comes to the 65816. I have never used it, and I am implementing everything more or less as I learn about it. Tons of mistakes are expected along the way, so any corrections are welcome.

I will do my best to go back over my posts and correct any mistakes to avoid spreading misinformation. I like to report my progress, no matter how small, but when it comes to the 65816... it is uncharted territory for me.
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Re: dromaius816 - a new 65816 emulator

Post by BigEd »

(If you do revisit older posts and make changes, please be sure to mark the edits, so it's clear that they have changed. Also, if you change something important, post a new reply to let people know that you've done that.)
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Re: dromaius816 - a new 65816 emulator

Post by BigDumbDinosaur »

daniMolina wrote:
...I am a complete beginner when it comes to the 65816. I have never used it, and I am implementing everything more or less as I learn about it. Tons of mistakes are expected along the way, so any corrections are welcome.

The 65C816’s operation is somewhat convoluted due to its dual personalities and dependence on status register bits to set register widths.  I had to grapple with all that as I learned how to program the beast.  For example, if the accumulator is set to 8 bits, the index registers are set to 16 bits and TXA is executed, where does the MSB in the X-register go?

The first year after I had gotten POC V1.0 running was a learning curve—I had tons of experience with the 6502 family going back into the latter 1970s, but no experience with the 816.  So initially there was plenty of crashing and resetting as I figured out things.  In fact, I ran it in emulation mode for the better part of six months.

That learning curve has continued as I write evermore complicated programs.  I have had to revise my thinking several times on how to best program the 816, especially in the realm of native-mode stack and direct (zero) page usage.  Also, interrupt processing in native mode is almost a whole separate topic.

As part of the learning curve, I have posed numerous questions to Bill Mensch when the hardware’s behavior didn’t seem to agree what the data sheet was saying...or not saying.  For example, it was he who advised me that toggling the ABORT input won’t literally abort the currently-executing instruction.  The data sheet is silent on that.  :roll:

Quote:
I will do my best to go back over my posts and correct any mistakes to avoid spreading misinformation.  I like to report my progress, no matter how small, but when it comes to the 65816... it is uncharted territory for me.

Not to worry...the 816 was uncharted territory for me when I designed POC V1.0. I read and re-read the data sheet until I was cross-eyed, only to discover that it had several errors (one in the opcode table drove me bonkers until I realized it was an error).  In some places, the data sheet contradicted the Eyes and Lichty programming manual.  Since then, data sheet errors have been brought to WDC’s attention and most have been corrected.

In terms of learning how to efficiently program the 816, the Eyes and Lichty manual remains, by far, the best source of information, with remarkably few errors for a manual of its size.  Although I have written many tens of thousands of lines of 65C816 code since beginning my POC project, I keep the manual handy—I have printed and bound it for convenience.  If you don’t have that manual, I urge you to get it.

The data sheet remains the best source for sorting out hardware details, especially the sequencing of instructions and what happens to outputs such as VDA and VPA as an instruction is sequenced.  The only thing to beware are the timings published in the data sheet, which reflect the die geometries of the 1990s.  The current production parts are much faster than the data sheet lets on, something I discovered with logic analyzer readings.
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Re: dromaius816 - a new 65816 emulator

Post by daniMolina »

Quote:
For example, if the accumulator is set to 8 bits, the index registers are set to 16 bits and TXA is executed, where does the MSB in the X-register go?
That could have been an interview question for some 65816 programmers position back in the 90s! With my current understanding... I'd say X's MSB goes silently into the Accumulator MSB, (or B).

If I've got it right. Setting the index registers to 8 bits clears the MSB, so if you go back to 16bits, MSB is zeroed. The accumulator is different and the MSB is preserved, and even acccesible with the XBA instruction, so in this situation, X's MSB will end up in B. Am I close? :wink:

I do have that book, just a PDF copy but... for its price, I will probably buy one. It has already helped me a lot.
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Re: dromaius816 - a new 65816 emulator

Post by BigDumbDinosaur »

daniMolina wrote:
Quote:
For example, if the accumulator is set to 8 bits, the index registers are set to 16 bits and TXA is executed, where does the MSB in the X-register go?
That could have been an interview question for some 65816 programmers position back in the 90s! With my current understanding... I'd say X's MSB goes silently into the Accumulator MSB, (or B).

Yer fired!  :D  Just kidding!

If the accumulator is set to 8 bits and the index registers to 16 bits, TXA will be an 8-bit operation, with the A-accumulator receiving the LSB.  The B-accumulator will not be affected.  The general rule with register-to-register copy instructions is the width of the receiving register determines whether the copy is 8 or 16 bits—with exceptions.  This behavior can be counter-intuitive in the case of a TAX or TAY instruction.  For example, consider the following code...

Code: Select all

         rep #%00110000        ;16-bit registers
         lda #$ab12
         sep #%00100000        ;8-bit accumulator
         tay

Running the above will result in .Y = $ab12, even though the accumulator was set to 8 bits prior to the copy.

The exceptions are TDC and TSC.  These instructions result in a 16-bit copy, regardless of the state of the m bit in SR (status register).  The C in the mnemonic is the hint that the copy is always 16 bits.

Quote:
Setting the index registers to 8 bits clears the MSB, so if you go back to 16bits, MSB is zeroed.

That’s correct, and is a convenient way to strip the MSB from a word.  It’s also a convenient way to introduce a bug should you forget that SEP #%00010000 affects both index registers.  :o

Quote:
The accumulator is different and the MSB is preserved, and even acccesible with the XBA instruction, so in this situation, X's MSB will end up in B.  Am I close?

See above.  The sequence...

Code: Select all

         rep #%00110000        ;16-bit registers
         lda #$fe98
         sep #%00100000        ;8-bit accumulator
         ldx #$ab12
         txa

...will result in .A = $12 and .B = $fe.

Speaking of the XBA instruction, it affects SR in a subtle way.  The n and z bits reflect the result of copying what was in .B into .A without regard to the condition of m.

XBA is handy for reversing endianess of a word.  I use it for that purpose in the SCSI driver in my POC unit’s firmware, as words that are part of a SCSI command descriptor block are in big-endian format.  That is also true of 16-bit data returned by a SCSI command, such the block size returned by a disk following an inquiry command.
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Re: dromaius816 - a new 65816 emulator

Post by daniMolina »

So there are rules, but they have exceptions, but they too have exceptions, but they...

It's time to get a real, 100% accurate emulator, so I can test every opcode, one step at a time.

Thank you for all those insights!
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