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PostPosted: Sun Nov 17, 2024 7:39 pm 
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Hello 0010 all,

First some data on the 8271 from Intel's Handbook (see also in attachments):
  1. For the clock at pin 3 of the 8271 4MHz is the only frequency mentioned
  2. DACK and CS simultaneous being zero is explicitly stated "Not Allowed"
  3. "For non-DMA transfers, this signal (DACK) should be driven in the manner of a "Chip Select"."

Now here are my questions:
  1. a. The Atom and Beeb use 2MHz, why the difference ❓
    b. Must the FDC clock signal be derived from the µp clock generator or may the FDC have a separate crystal oscillator ❓
  2. Is that "Not Allowed" not exactly what the Atom and Beeb do ❓ (see diagram below)
  3. Is this "Chip Select" how the Atom and Beeb use DACK and why it is pulled low together with CS ❓

Although this forum is called 6502.org I hope someone can help me out on the questions I have concerning the way in which Intel's 8271 FDC is used by Acorn.


Attachments:
File comment: Table from Intel Handbook and part of Atom FDC card diagram:
CS and DACK.png
CS and DACK.png [ 719.23 KiB | Viewed 105 times ]
File comment: Intel data available to me:
FDC 8271 Data Excerpt from Intel '84 Handbook Vol.2 (Complete ❓).pdf [8.4 MiB]
Downloaded 4 times

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Gr :D :D tings, Louis

May your wires be long and your nerves be strong !
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PostPosted: Sun Nov 17, 2024 7:57 pm 
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L0uis.m wrote:
Although this forum is called 6502.org I hope someone can help me out on the questions I have concerning the way in which Intel's 8271 FDC is used by Acorn.


It is all about the 6502 and we often discuss many old systems as well as our retro-new ones.

Have you looked at/Do you know about stardot though? It's highly likely there are more folks there who can help you.

https://stardot.org.uk/forums/

-Gordon

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Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/


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PostPosted: Sun Nov 17, 2024 8:24 pm 
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According to the Beeb circuit diagram, the 8271 clock is 4MHz.
see perhaps
https://stardot.org.uk/forums/viewtopic.php?t=17583
or
https://mdfs.net/Info/Comp/BBC/Circuits/BBC/bbc.gif


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PostPosted: Sun Nov 17, 2024 9:07 pm 
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Hello Gordon and Ed,

drogon wrote:
Have you looked at/Do you know about stardot though? It's highly likely there are more folks there who can help you.

I started a few threads on Stardot about the 8271 long before I registered here. Little reaction, especially about the questions I also posted here almost non. I think my questions are too specific to the 8271, nobody uses the 8271 any more and I fear interest in it has waned.

I also posted some at two sites where the de-cap of the 8271 is discussed, no reaction at all.

That's why I started this thread here . . .

BigEd wrote:
According to the Beeb circuit diagram, the 8271 clock is 4MHz.

In the Beeb diagram that I have there is an LS393 (IC86) that gets 16MHz or 8MHz (via link S27), the LS393 divides this by four (output QB), thus pin 3 of the 8271 can get 4MHz or 2MHz.

Apart from that, on the Atom FDC card the 8271 solely receives 2MHz on pin 3, which is the basis of my first question about the frequency.

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May your wires be long and your nerves be strong !


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PostPosted: Mon Nov 18, 2024 8:53 am 
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Joined: Thu Dec 11, 2008 1:28 pm
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Location: England
Perhaps useful to read
A Hardware Guide For The BBC Microcomputer where page 30 talks about S27 and the clocking of the FDC.
Quote:
Link S27 is used to route either the 8MHz (5 ¼ inch drive) or the 16MHz clock signal (8 inch drive) from the video ULA into one input of a 74LS393 dual 4-bit binary counter (IC86). The divide by four (QB) output of this counter provides the clock input to the FDC. Thus either a 2MHz or 4MHz FDC clock is provided, depending on which drive size is to be used.


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