pdragon wrote:
But from these traces it seems like any write strobe generated downstream of phi1 is going to be too slow to meet the 10ns limit after phi2? So I'm probably missing something!
I don't think you're missing anything. All that this means is that your design is out of spec according to the data sheet. Unfortunately, the data sheet is mostly fictional. Our universal lived experience is that HC logic works fine for this. Regardless of hold time, whatever was last on the bus will stick around for *milliseconds* due to bus capacitance. As long as your /WE goes high before the 6502 has started driving the bus *in the following cycle* you will be fine.
That being said, though, why not just use an AHC part and be in spec? The only downside is that your system might be able to go faster!
You have it set up like this, right?
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pdragon wrote:
So we want the rising /WE edge within 10ns of the falling phi2 one.
Looking at the 50% voltage point (is that right?), it seems like the bad case shows about 20ns between the falling phi2 and the rising /WE. There's about 10ns lag between phi1 and phi2 plus about 12ns lag from phi1 to /we, which seems about what to expect from the hc139's datasheet. So that's too slow to be guaranteed to lock the addr/data that the 65c02 is holding?
Keep in mind that the kind of glitch you are experiencing is not the kind of glitch that happens if your write strobe rises too late. If your write strobe rises after the 6502 has started changing the bus for the next cycle you may get the *wrong data* in the *right place.* Your glitch is the *right data* in the *wrong place* (or in multiple places). In other words, it's an address bus problem.
*Unless* (this just occurred to me) it's holding so long that the address lines have started to change from $01FC to $01FB. A0 and A1 will be '1' in $01FB, so if WE\ is still low when A0 and A1 have changed (but not the other address lines yet) the SRAM will write to $01FF. (Maybe a better way to say this is that the only difference between $01FF and $01FB is the A2 line. If A1 and A0 go high before A2 goes low *AND* WE\ is still asserted at that time, it could account for overwriting $01FF.)