pdragon wrote:
One thing I noticed while sketching was (a) Michael's drawing says "untested"
and (b) it's using the phi1 output for qualified read/write. I know the W65c02 datasheet says this is no longer spec'd/tested, so maybe it is lagging phi2 enough that it causes some problem when i'm accessing one of the IO chips immediately before/after RAM?
I doubt it. Michael's drawing says "untested," but many of them have been tested by me (
) and they work great! I haven't built this particular one, because I don't have any `682s, but I have built several very similar ones using `688s.
Although the WDC docs do discourage folks from using the Ø1 output in new designs, one of the stated purposes for these chips is to keep vintage machines running by replacing their old dead CPUs. Those old designs often rely on the Ø1 output. As Garth says in the Primer, it's silly (especially for retro hobbyists!) to abandon a 50 year old time tested design just because WDC has stopped a production test. The transistors are still there.
That being said, there's a better way to get a symmetrical two-phase clock, which is use a double-speed oscillator and run it into a flip flop (such as half of a 74AHC 74). Use the Q output as Ø2 and the ~Q output as Ø1. Like this picture from the
Primer:
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Quote:
RAM: AS6C1008-55PCN - i have a16 wired high, i'll try pulling low instead to use the other half but I don't think it's a memory problem.
Aha! That is the same series that other members have had trouble with. In the thread I mentioned it was a smaller capacity chip (the Alliance AS6C62256) but I wonders, I does. Do you have a RAM chip from a different manufacturer you could try switching out?
Quote:
demux - SN74LS139AN <= need to double-check but I might be mixing LS and HC here which is probably a bad idea
Yeah, unless you want to do a lot of thinking about what's driving what and adding strategic pullup resistors. Also, that `139 is doing a pretty important job. Ideally it would be a 74AHC (although HC will probably work fine at your 1MHz and slower speed).
Your wiring is beautifully tidy! I'm going to give you some suggestions. Unfortunately my "shop" is a wreck (thanks to being in the process of building an actual shop) so my electronics stuff isn't really available for photo demonstrations. I'll just have to try and describe verbally.
In the top, main part, of your system, you have power and ground rails running vertically. All the rails are connected together by horizontal rails at the top and the bottom, so your layout looks like a sideways ladder. That's good! However, there aren't enough horizontal connections between those vertical "rungs." Look at, for example, your `139. There's a short black jumper that connects its GND pin to the GND rail on its left side. You should add a longer black jumper that connects that same pin to the GND rail on its right side (where the two yellow wires are running). You should do that for every IC so that instead of it being like your chips are hanging off of a ladder, it's like they're living in a grid with a resolution of one "GND square" per IC.
The other thing is that your bus wiring generally runs horizontally, while your power wiring generally runs vertically. Ideally, wherever you have those horizontal arches of signal wires, there would also be arches of GND wires - one every other signal wire. That might not be practical, but you could try adding one or two GND arches per bus "bundle," especially to the ones that sort of "submerge" in the breadboard to go under some other signals and come out the other side. When I'm doing breadboard wiring I try as much as possible to have the signal wires running directly above the power rails. If they have to cross a breadboard I put a power rail there using jumpers.
Here's a picture of one of my projects:
download/file.php?id=20708&mode=view If you look at all the little green jumper wires you can see how every IC has a row of them right next to its GND pin connecting the adjacent GND rails. If you look at the white signal bus wires right in the middle of the board you can see that right under them is a vertical row of green staples so that there is a GND path that directly tracks them.
Edit: One really important thing I meant to mention and forgot to include: your clock signal is REALLY long. Give it its own dedicated ground wire that runs right next to it over the breadboard surface, and where it's airborn make it into a twisted pair of CLK/GND. Your clock module only has ONE connection each of GND and VCC. Do the same thing to it as to the main part of your system (give every IC a connection to both GND rails) and then connect its top rail to the main system's bottom rail 4 or 5 times along its length (basically, wherever one of the ladder "rungs" connects to the bottom rail of the main system).