EPM240 development board is an inexpensive (<$10) CPLD board with 50MHz oscillator. It has four 2x20 headers to breakout all CPLD I/O that also serve as connectors for mezzanine board. EPM240 is a 3.3V CPLD, but input to the board is 5V which is regulated down to 3.3V. EPM240 has 240 logic elements or equivalent to roughly 192 macrocells; it also has 8Kbit of internal flash that can serve as the bootstrap ROM. All my designs in EPM7xxx can easily port to EPM240; this is a significant step up in capability from my 64 or 128-macrocell EPM7xxx CPLD.

I've purchased a number of EPM240 dev boards to experiment with retro computers. I have made pc boards for Z80, 6502, and 68SEC000 and plan for Z180 and 68EZ328. Z80 mezzanine development is successful and completed; I have done a cursory test of 68SEC000; and I'm currently focusing on 6502 which is the topic of this post.

The project is called 3V6502. The design is based on "6502 as VGA controller". The hardware is a mezzanine board plug on top of EPM240 dev board. The mezzanine board has W65C02 operating at 25MHz and 128K RAM in two banks. On paper W65C02 is rated at 14MHz at 3.3V. While it is likely capable of higher clock operation at 3.3V but to help with 25MHz operation, there is a local regulator with its voltage output adjusted to 3.5V. The slightly higher voltage is not a problem with 3.3V CPLD which requires the input voltage to be within 0.3V of the 3.3V. The design goal is a standalone computer with PS2 keyboard, 640x480 monochrome VGA display, serial port, and SD card for mass storage. Optional features are I2C interface and realtime clock.

Operationally, the 6502 boots out of CPLD's internal flash which initializes SD card and loads system code into RAM. The 25MHz 6502 spend 90% of its throughput driving the 640x480 display; it is the well-known beam-racing algorithm where it services the 31.5KHz interrupt from the horizontal sync and output 80 bytes of video data (640 pixels) to an 8-bit shift register that drives the display at 25MHz pixel clock. During the horizontal retrace period, it also looks for PS2 keyboard input and serial port input. The processor is fully utilized during the active video phase, but every 16.7mS video frame, it has 1.4mS of vertical retrace period where it can do real work. It is not much time; it is effectively a 2MHz 6502 when it is not busily doing video and keyboard processing.

The VGA beam racing is an old concept; what is new-ish is operating 25MHz 6502 at 3.3V which can directly interface to more capable CPLD/FPGA and allow more advanced features.

to be continued
Bill

Attached is schematic of 3V6502 rev0. It is a simple design with W65C02 hooked up to 128K RAM in conventional fashion. There are two banks of memory with $0-$3FFF as the common RAM. The ROM is reside in EPM240, so is the serial port and decoding logic for RAM, and peripherals. The top 1K ($FC00-$FFFF) is ROM inside CPLD; next 256 bytes ($FB00-$FBFF) are I/O; and remaining memory ($0-$FAFF) are RAM.

The rev0 PC board is 2-layer, 3.5"X2.2". There are several layout mistakes, the most obvious one is PS2 connector is pointing inward rather than outward. The fix is tilting PS2 connector 30 degree to clear the RAM as shown in the side view of the 3V6502 & EPM240 stack-up.

For testing purpose the EPM240 contains a simple bootstrap ROM that loads a hex loader into RAM from the serial port which, in turn, loads applications into RAM. The hardware runs OK at 25MHz @3.5V, passing memory test and able to run various applications reliably. There is a particular application I want to run which is a simple monitor that takes input from PS2 keyboard and execute few basic commands such as display memory, modify memory, and run from specified address and display the results on VGA monitor. While it is functionally simple, it requires PS2 keyboard entry and VGA beam racing to work correctly, that fonts are rendering correctly and screen is scrolling reasonably fast. The attached animated GIF shows this application running as captured by VGA video capture hardware. The first character of each line is not shown because the clock is 25.0MHz instead of the standard 25.175MHz. I can adjust the monitor to compensate for that, but the video capture hardware is not adjustable.

The hardware appears to be working, but there are significant software works ahead. I need a SD card bootstrap code to initialize and load program from SD card. I also need to revamp the software framework to run meaningful applications during the short vertical retrace time. Porting EhBASIC to this hardware will be the next challenge.
Bill

Still working on the 3V6502 project. I'm able to boot from EPM240's internal flash and run an Intel Hex loader. The internal flash is basically a serial flash so it is quite slow, about 5uS per byte access time. It is necessary to copy the program from flash to RAM and run it in RAM. Because the interrupt vector also resides in flash, interrupt response is slowed down by the slow access to interrupt vector at $FFFE and $FFFF. So I've added a ROM disable feature to replace the internal flash with RAM.

Currently I'm working on a SD initialization and bootstrap routine for the flash so it can load and run programs from SD card.
Bill

The internal flash in CPLD can now initialize a SD card, load and run a program stored in the SD card. This SD initialization and load routine is 425 bytes so it fits nicely in the 512-byte CPLD internal flash. The hardware can now power up, load and run any program stored in specific sectors of SD card. For software development purpose, it is running a monitor program that can serially load and debug application software.

The application software I'm currently working on is yet another monitor program except it takes input from PS2 keyboard and displays output on a VGA monitor. Functionally it is the same program that I've shown in July 24 post of this topic except its internal organization is completely different. It is now an interrupt-driven foreground/background program. The PS2 input and beam racing video output are interrupt driven tasks performed in background while an application is running in the foreground. The foreground task is being interrupted at 31.5KHz, worse yet, a big chunk of the time, 15.3mS out of every 16.7mS, is used exclusively for displaying of video data, so the foreground application only has 1.4mS of CPU time every 16.7mS. Despite of that, it all appeared to run smoothly. From software development perspective, as long as the foreground program does not directly deal with interrupts, it can be written as a standalone software completely unaware of keyboard/video activities in the background. While 6502 is 25MHz, the CPU throughput available to the foreground program is only about 2MHz so for self-hosting applications, it may make sense to stop the video/PS2 processing in the background and devote the entire 25MHz 6502 to compile a program. The screen will go blank and keyboard unresponsive during the program compilation, so perhaps it makes sense to turn on the keyboard/screen periodically to display status and receive user input.

Let see if I can port EhBASIC to this hardware.
Bill

Revised the 3V6502 pc board to correct the orientation of PS2 connector. This is revised 3V6502 driving monochrome 640x480 VGA display and receive input from PS2 keyboard. It also has a 115200N81 serial port. A homepage for 3V6502 is under construction here.
https://www.retrobrewcomputers.org/doku ... 2:3v6502r1
Bill

3.5v regulator? That surprises me - a typo?

Neil

I was worrying W65C02 may not reliably run 25 Mhz at 3.3V, so the local regulator is adjustable to provide 0.2V extra voltage above 3.3V. 0.2V higher does not violate the max IO voltage of 0.3V above V33 for interfacing with EPM240. My worry may not be warranted, so the local regulator may be removed when I have more experience.

Ah, I had wondered if it were something like that. Thanks.

Neil

What a wonderful system! I totally love it! Especially the fact that it's twice the speed of Apple ][ after blowing 90% of CPU on display.

Although I feel Woz would've somehow found a way of reclaiming at least a few cycles from that budget.

Hi Bill Just ordered some PCB's will try this out when they arrive. Interested that this continues the VGA experiments not just another maximum speed 6502 (without the video aspect). I'm always amazed that you keep pushing to see what new things you can do with the mix of new and retro hardware.

Hi Larry,
I updated the 3V6502 homepage to include all information I have on 3V6502 rev1. While going over the build of materials document, I found EZ1588CM is an obsolete part. I believe LT1117CM is a suitable replacement, but I have not tested it. Another problematic part is fast 10nS RAM in DIP32 package--it does not exist. I have mounted a 10nS SOJ on DIP32 carrier board, but I don't know whether you have such carrier board. If you don't have one, I can drop one in the mail to you. Lastly, the SD boot flash only work with 2GB or smaller SD cards. If you only have a larger than 2GB SD cards, I can change the boot flash to accommodate it. The software to accommodate many generations of SD cards are too big to fit the 512-byte flash, so I may have to publish several versions of boot flash for different generations of SD cards.
Bill

Thanks for the update Bill. I located some EZ1588CM although I probably paid a premium for them. I do have this board (https://www.retrobrewcomputers.org/doku ... rds:no-ps2) but I'm not sure about the pins you used and I am concerned it might be too wide with the extra row of pins. I could try trimming it though. I have a couple of small capacity SD cards (Full size) and I am using a 2GB microSD in the Z80 version so that should be fine for an initial try. Boards have shipped but are on the slow boat for delivery.