OwenS wrote:
I can't say I know the specifics of the bitstream format; that changes per device since its really just a dump of the device's configuration RAM and therefore unstructured.
. . .
The commands for downloading bitstreams to the device are documented. As said, OpenOCD can download to Xilinx FPGAs.
You contradict yourself with respect to what I'm talking about. You first admit you don't know the bitstream format sent to the device, and that it changes per device. Then you say, "But, OpenOCD can program it! Use that instead!" You're
completely missing my point.
The dump, of course, is
not unstructured (it's actually
rigidly structured, which is why it has to change with every chip design), but it is instead opaque. The details are not public -- only Xilinx software knows how to generate the bitstream for Xilinx (supported) parts.
That is my beef with the FPGA industry.
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Where on their website is this instruction set documented? Heck, where are the datasheets?
They're a new company started by the developers behind the Intellasys product-line. See
http://www.intellasys.net/index.php?opt ... &Itemid=75 .
The reason GA exists is because of severe IP rights fall-out between the venture capital firm backing Intellasys and the (now former) senior management of Intellasys. Lots of lawsuits. Lots of hard feelings. And a VERY REAL possibility that this technology will NEVER see the light of day.
I really, really, really hope it doesn't come to that. And, you shouldn't either. Lots of companies like BMW and Sony were lining up to grab ahold of these chips, and very cheap eval kits were on the horizon just before this all started to happen.
At any rate, I have Intellasys chips in my possession. I've coded for them. VentureForth is a somewhat specialized version of Forth Inc's SwiftForth pre-programmed to work with Intellasys' parts (with full source included, I might add, though it's not technically open source).
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Where do I get a standard toolchain for the device? (In the case of an MCU, the de facto standard toolchain would undoubtedly be a C compiler & linker)
You cannot use C to write software for these cores, because they are 18-bit stack architecture cores with only 64 words of RAM. You'll need to learn to use Forth.
But, if you think you can pull it off, the details of programming the chip are included in the online documentation. Have at it. They don't care, and even encourage it.
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While there are deviations - as there are for all multi-vendor standards - in general it is possible to write a portable design. Most of the vendor-specific stuff is so documented, and primarily there to allow you to optimize (E.G. blockram or multiplier primitives)
If you're really in the market (and not a hobbyist), you don't choose Xilinx and then stick exclusively with generic Verilog. If you're going to differentiate your products on the market, you're going to use everything at your disposal to do so, which directly translates to, your products will become hard-dependent on vendor-specific extensions.