Hi BigDumbDinosaur, yes I understand it was just that the simulation software I tried did not have the functionality to simulate this circuit properly. But after Jeff's great explanation I don't have to anymore .

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

I have a 74HC245 in my schematic to output the 8-bits from the keyboard. I connected the direction pin to the OUT signal (pin 5 from the 74151) that is a mistake I can just pull that high so that the direction always goes from A to B. I can connect pin 5 from the 74151 to the CE pin via an inverter to enable the chip if a key is pressed.

Is this the way to go? The OUT signal is also send to the W65C22 (CA1 or CA2). Do I need the 74HC245 at all or can I just hook up the 8 bits straight to the W65C22?

Another option is to use And gates that output the 8 bits if the the OUT signal is high (bit 1 AND OUT etc.). But then I need 2 chips instead of one.

What do you guys think is best? Perhaps there is even a better solution I did not think of.

*edit

I'm not sure if this is a problem but maybe these bits need to stay on the bus for a while? I can imagine that if the clock pulses the data is gone before the 6522 had time to process the date. Or wil it be fast enough to read the data before going to the next column/row?

*edit 2

I need to read the datasheet and the timing diagrams in there before asking. I try to understand it, in case I don't I will get back to ask questions.

Ok, I have had a read and I think I need Read Handshake Control for the 65C22 to read in the data from the keyboard.

The datasheet tells about the Read Handshake, the Read Handshake signals the 65C22 that data is ready on the peripheral port this is done by sending a signal to the CA1 interrupt input pin. So I need to be sure that the data is available before sending this signal. The 65C22 sends a 'Data Taken' signal back via the CA2 pin when the 65C02 reads the data.

This does answer my question unless I did not understand it well. But then I need to figure out how to accomplish this. I could add a latch (the 74573?) to keep the data active until I get the 'Data Taken' signal back from the 65C22. The OUT signal in my schematics will be high and then the keyboard outputs data from the 4-bit counters and the shift/control somehow. So I can't use that as a signal to the CA1 pin I guess? So I need to trigger a signal after the content is in the latch.

If I use the 74573 I need to keep the output enable low until the 65C22 sends the 'Data Taken' signal somehow.

Did I understand everything correctly? And what are the steps to take to get the timing right?

Do I need Read Handshake Control at all? Or can I just use the CA1 pin to trigger an interrupt and let the CPU fetch the value from port A of the 65C22? In that case I still need to hold the value for a while via a latch?

I was thinking about this. If I keep one port dedicated to the keyboard. I can always output the control/shift and clock values. Then I would be able to use the OUT as a strobe signal. Would this work?
Or is there a better way to do it?

I wonder why I don't get an answer to my questions. Perhaps my question is not clear. What I want to know is the following.

If I put data on port A of my 65c22S and then send the OUT signal coming from the 74HC151 (Y) when a key is pressed to CA1. Is this enough for the 65c22S to be able to read the data from port A? Or will there be timing issues? Or do I need extra circuitry to be able to pull it off?

I think the CA1 input can cause an interrupt, and your service routine can then read Port A. That will be some time later, so no need to worry that the data won't be ready. But you do need to ensure the data will still be there. I don't think the 6522 automatically latches data on the parallel interfaces - but check the datasheet to be sure.

In the datasheet I found this:

When reading the Peripheral Port (PA or PB), the contents of the corresponding Input Register (IRA or IRB)
is transferred onto the Data Bus. When the input latching feature is disabled, IRA will reflect the logic levels
present on the PA bus pins. However, with input latching enabled and the selected active transition on
Peripheral A Control 1 (CA1) having occurred, IRA will contain the data present on the PA bus lines at the
time of the transition. In this case, once IRA has been read, it will appear transparent, reflecting the current
state of the PA bus pins until the next CA1 latching transition.

I'm not sure but is this what you mean?

Oh, good find, I was mistaken - it seems the 6522 can use those inputs to control latching of the input bus.

In which case, the nanosecond-level timing is important: you need that strobe to fire when the inputs are suitably stable.

The two 3-bit counters control the 74238 and the 74151. The output of these counters will be at port A. The Y output of the 74151 will be the strobe signal to the CA1 this will happen if the user pressed a key. So the strobe will happen when the values of the counters will already be on port A. I guess I just need to test it on a breadboard/perfboard to see if it works.