ok yea, 4 layer board are quite a bit more expensive. while 10x10cm is the cheapo limit for 2 layer, it's 5x5cm for 4 layer. still my 65816 is exactly 10x10cm and a 4 layer board. so it was a bit more expensive.
Jmstein7 wrote:
Ha! I'm struggling to get past 8mhz! And I'm using 55ns Flash Rom, as the EEPROMs I was using didn't get below 100ns; but, everything is hand soldered. What RAM and ROM are you using to get to 20mhz? I didn't know it was possible to get past 14mhz, or so.
the 65xx chips are insanely overclockable, and the datasheets are usually pretty... pessimistic with their limits and timings. i usually just eyeball timings anyways... for my SBC my thought process was: 10ns RAM, 10ns CPLD, 25ns for half a clock cycle at 20MHz, 25 > 10 +10 so it should work. and it did!
for RAM i'm mostly using the
IS61C5128AL-10KLI, 512kB and 10ns access time but using a SOJ package (SMT) so you are forced to solder them onto an adapter or directly onto a board. i've also started using the W241024AK and W24512AK, which are old-stock 128kB and 64kB SRAM chips respectively. both in DIP packages and with 15-10ns access times so they're perfect for compact and fast 65C02 or low-end 65816 Systems.
for Flash/ROM i'm probably using the same chips as you. the SST39SF0x0 series but as PLCC because they're smaller than the DIP ones. as for speed i just slow the CPU down whenever it accesses ROM (or IO). so while executing from ROM it basically runs at half the speed, but as soon as it loads a program into RAM and jumps over to it, it goes at full speed (which is currently only 16MHz with an expansion card installed. remember to always put buffers before any external connector when you go at high speeds!)
Jmstein7 wrote:
As to autorouter, what does that workflow look like? I HATE routing manually. Hate it. It takes me forever, and I'm always guessing with trace sizes and VIAs and all that. I've also only used double layer PCBs.
i mean if you want the full pipeline:
- First lay down the idea of what i want this design to do, what main components (CPU, RAM, ROM, etc) it will use
- Then make a basic layout of the logic to see if it fits (pin wise) onto a 44/84 pin CPLD
- Afterwards either start making the logic design (if it's very simple) or start making the schematic
- Try to work out any issues that arise while making the Schematic (mainly just planning mistakes where i miscounted how many pins i would need on a CPLD or VIA or something)
- Once the Schematic is done, i start with the PCB. enabling the ratsnest and just start placing things, aiming for compactness while keeping the ratsnest as untangled as possible
- After i'm happy with the layout, I add some rounded corners and screw holes (round corners look cool and screw holes are useful for standoffs as laying a PCB down can mess up a table with the pointy solder joints and stuff, or you could short something!)
- Export the whole thing as a spectra file, import to freerouting, let it run while i watch YT or play games. once done re-import it to KiCad and do some minor cleanups and add some copper pours and via stitching (no idea if it helps with performance but i just think it looks neat)
- Finally if everything looks right and i didn't mess up any connections (that i know of) i add the JLCJLCJLCJLC silkscreen somewhere where i don't see it. export the drill files and gerbers, throw them into a zip file, upload to JLC, make the PCB black because black is cool, and then add it to cart.
tada, a fresh PCB is done!
plasmo wrote:
With sufficiently fast RAM, W65C02 can reliably run 25Mhz. Don’t need slow ROM, you can bootstrap out of fast ROM in CPLD or 22V10.
technically yes, you can put a small botloader program into a CPLD and use it as a high speed ROM, but it depends on the use case i would say.
for example if you pla on having an expansion connector and want to hook up IO stuff that you know are too slow for the CPU at full speed, then you have to implement a wait state/clock stretching circuit anyways and at that point you might as well safe yourself the Macrocells and use a seperate ROM chip.
or maybe space is insanely tight and your ATF1504AS or whatever was just enough macrocells to throw in a 64 Byte bootloader for a CF card or something, then you of course safe yourself a whole extra chip.
or you could have a board with an onboard microcontroller like a ATMega or CH32Vx which is used as IO controller or co-processor. in which case you have it take over the bus after reset and preload the RAM with a program before releasing the CPU. which also saves you a ROM chip.
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