After great frustration, and some time away, I'm going to try and return to a W65C816 project I've been working on:

http://forum.6502.org/viewtopic.php?f=10&t=7925#p105877

Long story short, I decided to go back to a basic W65C816 SBC with 32K RAM, 16K ROM, and an ACIA, just to play around with the chip. I'm also trying out CPLDs for the first time. I picked up an ATDT1150USB isp cable and a bunch of ATF1504AS, 10 ns, PLC44s. As a test, I've connected all the GND and VCC pins, as well as the JTAG pins to the ATDT1150USB. I downloaded ATMISP and verified the connection and erased the chip successfully a few times. So, I have the JTAG connection and programmer working.

I see a bunch of pins on the ATF1504AS aside from power and I/O, such as OE2, GCLK2, GCLR, OE1, GCLK1, GCLK3, PD, etc.

Which, if any, of these absolutely need to be connected? For my purposes, all I want to do - for the moment - is hook up A8 through A15 as inputs and scalar RAM, ROM, and ACIA enable outputs.

Thereafter, I'm wondering how difficult it is to use WinCUPL? I know Verilog, but I don't seem to see any way to, say, set up a bus for the address lines (8-bit) for decoding. For example, in Verilog I might do:

assign RAM_enable_n = ~(address[15:8] < 8'h80);

I don't see any way to do anything like that.

Jonathan

Before plasmo jumps in I would recommend looking at his CRC65 in the 65816 version for some inspiration.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks, BDD. Actually, the current design is a warm-up exercise. I want to get to learn how to use these handy dandy little chips. Ultimately, I’m going to want to use it to latch the bank address and data lines. I read somewhere that I would need the 7ns version for that. I don’t know if that’s accurate - I’m using the 10ns 5V variant.

And, winCUPL - it’s weird. Is there any way I can do this using Verilog?

Thanks!

Jonathan

No verilog for WinCUPL, not even schematic entry. Its design entry uses the original sum-of-product logic expression.

If I were designing ATF1504 with WinCUPL (quite unlikely), I would draw out the design in schematic and then translate it into sum of products and use PINNODE for buried flip flop. It is painful. I rather design in Quartus in either verilog or schematic, then translate to ATF150x using POF2JED.

Since you already plan to use ACIA and ROM, I agree with BDD that you should first design a working system with PLD such as 22V10 and connect CPLD in parallel to learn about it. Then you can gradually transfer the functions from PLD to CPLD. You can eliminate external functional blocks like ACIA and ROM as you transition to CPLD.
Bill

ChatGPT suggested this code for WinCUPL:

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

This thread covers a couple of options for using Verilog with ATF15xxAS parts:
Verilog to WinCUPL generator\workflow

Dave

Thanks Dave!

Wow! Thank you, BDD. That makes more sense. And, thanks for the manual.

Jonathan

As always, thank you, Dave! How are your projects going?

Jonathan

Hi, Ed. Long time!

Jonathan

How about this?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

It worked. So, that's good.

For the GALs, they're also JTAG, right? I don't have to get another programmer? They're kind of expensive.

I saw ProChip Designer on the Microchip site, when I was getting WinCUPL and ATMISP. Is that any good? It seems to permit the use of HDL, though I guess you have to buy a license if you want to synthesize anything? Doesn't that sort of render it useless?

EDIT: I was just browsing on Mouser and I saw the following:
ATF750C-7PX
ATF750C-7JX
ATF1502AS-7JX44

The last one being a "cut down" version of the one I'm using (but 7.5ns)

Do these have enough to demultiplex the Bank Addresses from the Data lines, while also decoding addresses?

I looked at the datasheet for the ATF750Cs, and there is nothing about programing them.

Jonathan