Short: Device to simply and atomicaly set/reset single bit output informations

Problem:

I need (for MC68B50 - ACIA) way to set "Ready to Read" flag to pause incoming serial data until I make space in buffer. As input data may be 32kB+ IHEX which need be burned to EEPROM (slow for HW reason) it is not good way to reserve buffer for that all time, much better is to controll trafic, but MC68B50 does not have pin, which may be set to signal "Stop sending data to me, but continue listening to me sending data to you". So another way to communication is requiered.

Also I want to have more Serial in my future computer.

And there are other similar data, like Caps Lock, Num Lock, SD card active, "waiting for keypress", "reached debug point". Usually set somewhere in code and reset somewhere else. Maybe in interrupt too.

So it should be easy to set/reset just one bit. Clasical Read current status of port - Modify just my bits - Write new value to port keep risc of being interrupted by interrupt, which will manipulate the same port for other reason and after return to user code the Write part will push old data, efectively discarting the changes made by interrupt.

I am planing to make such "expansion card" or "I/O device" or what, which solves it.

There is Port A consisting of 8 R-S fip-flops and two adresses. Writing to the first (...00), it reset the R-S where are bits set in written value. Writing to the second (...01) it will sets the R-S where are bits set in written value.

So the task is easy - just write bit(s) which should be set (or reset) and it will be done in one instruction. So reaching debug point and detecting CapsLock in keyboard interrupt at the same moment will simply set both, in any order.

Here is my schematic (it uses 74HC ICs - '138 decoder, '245 bus, '279 RS and '04 NOT)



It also enable reading current status at the first address (...00) and read another 8bit input (from other external devices) on second address (...01) - because I had free address to use and more inputs are good anytime.
And it can have also Port B, same as the described, just on addresses ...10 and ...11

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I hope it would work, but also I am curious, if something similar was not developed before and released as single chip solution (similat to VIA, PIA, ACIA and others).
And also if somebody will have spot some problematic point on it, or places, which could be improved. Or if it is even good idea or is there better approach to the problem.

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What's an additional VIA among friends, anyhow?

@gilhad I believe you may run into problems as the - if I got it right - the '245 are open during the whole phi2 high phase.

However, the data lines only get valid shortly before phi2 goes down, at least they are not guaranteed to be stable for the full phi2 high half cycle. Thus you may find stray low pulses on your '245 outputs - changing your RS flip-flop state where it shouldn't happen

André

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Yes, my plans was to have those '245 open when phi2 is high, plus/minus delays from glue logic.

Also I did not think about this details and somehow hoped, that everything will somehow go smooth (and had feelings, that data are for me valid thru the full phi2 high time, but reguested from me just before it goes down).

So I looked into my datasheet to make it sure. But if I read the time graphs right (which is not guaranteed and I may read them totally wrong - and I would like to be corrected especially in this case), then there are two distinct cases:
- CPU want to write data to "device" (memory, I/O, ...) and then the data originate in CPU and CPU promise them to be valid at worse tdws (Write Data Delay Time = 55ns for my 4MHz R65C02) after the phi2 rises (or sooner, if I am lucky) and some time after phi2 falls
- CPU want to read data from "device" and then tha data originates in device and CPU requiers from me to promise, that the data will be valid at least tdsu (Read Data Setup Time = 30 ns for my 4MHz R65C02) before phi2 falls and at least thr (Read Data Hold Time = 10 ns for any R65C02). With minimal phi2 high cycle around 110 ns it is the "shortly before phi2 goes down"

And I will try it on the 6502 way later, now I am trying to set it up for HD63C09, but the E clock there is really similar to phi2 on 6502. There are some differencies, like extra Q clock (which lead before E and makes address lines valid way before E rises, which on the other hand restrict the DMA done on phi2 low - which is out of my reach at this time anyway) and little more instructions and registers, also some details, like which flags what affects, but on HW side they are nearly compatible - at least for simple "devices and othe expansions".

But still this are things, which I should considered before and I did not considered at all. So pointing it out helped me anyway. And I should consider this especially, when I will get to making some more elaborated constructions (like sharing parts of RAM between 6502 and Arduino, while both will be running.)

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WOW!
I had feeling, that my approach is somehow clumsy with 9 chips and 16 rezistors, but about possible improvements I could imagine just something small (or dedicated chip especially for this purpose - like those PIA, VIA, ACIA ...)
But your solution is just nice minimalismus with only 3 chips doing basically the same and have even better SW interfacing

It took me couple of hours to understand it and its implications, but it was really happy and instructive time!

You were totally right, that for such problems setting just one bit is enought and that doing it while preserving ALL registers is very nice way.
(And for reseting it while running program I can just connect one output to '259 CLR and write there 0 and then 1 - or simply write 0 to every outputs - early in the boot it does not matter so much and later I do not see much reasons to manipulate more outputs at the same time.)
And while I was initially scared about using addresses for 8bit register, I later realized, that it is not 8bit range (0..255), but 8 bits to set (0..7 times two).
And the 4 Chip Select pins are also nice touch }and it is easy to expand with CS3 attached to (say) A5 and even more with switching phi2 with CS0 (and setting it to A6), but then I realise, that I cannot today imagine so many I/O needed this way (as I am going to use also VIA (for timers and SR) and PIA (because I already have it and there is so much LEDS and other trinkets to put there )

And the trick with BIT to save register in reading is also really nice - I was not aware, that it uses N+V this way - on 6309 all flags are set from the result (so there I would just sacrified register as I would with my construction, but with LDA it will set the N flag apropriatelly, so no needs for testing the value anyway (and the "trash" on bits 0..6 do not anything and the register can be forget just after first branch))

It was really pleasure to try decypher its working and find so many diamonds on such small place

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Hmm, that all sounded good to me, it's a description of how all timings are referred to a falling edge of phi2 - either the falling edge which starts the cycle, or the falling edge which ended it.

But then you added one sentence

which I don't understand at all! I wonder if this is a mistake in understanding, or a mistake in explaining?

Looks like you have solution(s)

(Just add a VIA )

In my 6507 project I wanted an 8-bit output port so the board would run without the (optional) VIA and I used a 74x573 connected directly to the data bus with the latch input coming from the address decoder GAL.

But that's output only - so I keep a software copy in ZP so I can fiddle with the individual bits. Works a treat for what I needed it for (4 LEDs, 3 eeprom bank select bits and serial output)

-Gordon

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Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

I probably wrote it wrong or misleading.

It is all about my R65C02 4MHz datasheet, which states, for 4MHz for phi2 following minimal values:
Cycle time 250 ns
Low pulse width 100 ns
High pulse width 110 ns
and maximum 12 ns for clock rise of fall - which added together is 100+12+110+12= 234 ns of 250 in some guaranteed bounds, leaving 16 ns for low or high phase of pulse be little longer. (Nothing special, it is 4MHz digital waveform.)

And with 4MHz in head those stated "Read Data Setup Time = 30 ns " sounds to me exacctly like what fachat described "However, the data lines only get valid shortly before phi2 goes down, at least they are not guaranteed to be stable for the full phi2 high half cycle."
And so I wrote, that the statement is probably about Read timing, where I am supposed provide valid data for CPU at least 30ns before and 10 ns after falling edge of phi2. (so of the 110 ns of phi2 high it is first 80 ns there may be chaos/"do not care" on data lines, and then 30 ns there must be my valid data)

While in write cycle the CPU provide valid data for me for me for more than half of the high phase of phi2.

(Uh, still sounds risky, when reprased this way. Anyway I will go with GARTHWILSONs solution, which is much better, than what I hacked together AND it have no risc included.)

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I wonder if you have enough decode in your GAL to copy to zp in the same write? (i.e. make the output port appear as a zero page address for both write and read status.)

Neil

Thanks for clarifying, gilhad. Indeed all seems right - I agree with your analysis. I did check the datasheet, and note that you're quite right to add the rise and fall times to the high and low periods. (I might have guessed otherwise.)

Hmm... Currently:



So if I can create a spare pin on the GAL then I can map the button to $F0, bit 6, leaving bit 7 as serial input, then it frees up $F8 to be written to RAM at the same time as the hardware then read back from the RAM only.

It would be an interesting optimisation - save a double write when I update a bit and return one byte of RAM... (Not that there is any more code space for something to use it...)

I'm on the cusp of doing a PCB re-spin for it too, but I still have the original bread-board setup, so maybe I can play there..

Cheers,

-Gordon

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

Doing it the old fashioned way, it occurs to me that I'd probably be decoding a page zero anyway. So the next five bits wouldn't be much more effort... so any normal memory write to the appropriate part of zero page would just tickle an extra clock to the latch, which is hanging on the data bus anyway.

As you say, the button input can live at the same address as the serial input. You don't need to worry about keeping things in sync, it happens automatically.

Neil

A few thoughts come to my mind with this.

1) The 6850 appears to already have RTS and CTS pins that can be controlled with a register on that IC. I think that's what you're looking for. (Assuming I'm not misunderstanding what you need)
2) From your diagram, it looks a lot like you can do something very similar using the 6522. Might be worth while to see what that IC is capable of before designing a large board to solve the problem.
3) Another option might be to use the SC26C92 UART instead. It has a set of input/output pins intended for general purpose IO and flow control.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thank you for response

1) Yes, it have this pins, but devil is in details - the chip came here from prehistory, when Tyranosaurus Rex was autodialing modem over steam powered, paid and unstable telephone lines and then it was just perfect
- the CTS is OK - it is input pin and when The Other assert it (effectively saying "be silent and listen to me" ), my Transmit is blocked (and for me it looks like sending the last character is taking forever - until CTS is disasserted and I can talk again) - perfect, easy, convenient
- the RTS (Request To Send) is meant to power down the modem (and end call and save money and free line for peaople to use it) and so when it is asserted, it automatically prevent the chip from sending interrupt, when Transfer is complete (remember - modem is power down, nobody to talk to)
- but I would like to have something like "reverse CTS" to say The Other "YOU be silent and listen to ME", when the data came faster, than I can process (or buffer). And be able to send all responces to all requests, that The Other send me so far. And then again let The Other to speak more. There is no modem to hang up, there is not charge for the meter long cable to the PC on the same table, but small 8bit cannot run as fast as mighty 64bit is able dump its memory over line.
So the solution is get other output pin somewhere and connect it to CTS on other side (where my RTS would be, but I do not want also silence myself). Yes, The Other is probabely moder era and take RTS as complement to CTS. Sadly my 6850 is ancient and in its HW it still expect steam powered modem or something like that.

I suppose, that on new ICs (from this millenium, not last one) the RTS/CTS works exactly as I would need. But I want put to use, what I have at home in this case.

2) Basically yes, I do. 8 bit output, 8bit input, both times two (with Port B). But details are a bit different again
- this setting enable to set or reset just one bit, without possibly affecting others, in one atomic instruction (so also safe from interferrence from interrupts). In easy way: put in A which bits are you want (set the bits 1, others 0)
- write it to Set Register. Coresponding bits will go up, all others will stay as they are
- write it to Reset Register. Coresponding bits will go down, all others will stay as they are
no need to Read all bits before hand, then Manipulate just those interesting for this code and then Write it back (and risk, that some interrupt will change things in between)

It will may be worth to use 6522 instead with some overhead and wasting lot of its potential, but this idea looked for me as simple (before I start to elaborate on it). I was also curious, if some chip with Set-Reset single bits does exist. And I was also curious, how good or bad this idea is.

The result is, that the idea may work, but is overly complicated and there are way better solutions to the problem.

GARTHWILSONs module is far better approach and solves everything I wanted to do with my module in only 3 chips (and can it double or quadruple with bonus of reusing the '138). So I will go this way.

But Southern California (USA) is nearly on other side of globe, than Prague (Czech, Central Europe), and the postage would be probabelly way higher, than the prize of the module itself (and also I will have probabely problem to find good pay method). Also I want incorporate this to my computer as one of core parts, so I will that Grath Wilson on first part of his generous offer, as I had at home nearly everything, except the IDEA and I can easily connect such simple circuits.


3) Yes, it would be probably too good option, but I would like put my 6850 into some use and also I want start playing with it soon, but any improvement takes me at least few day of study and aditional plannig, so I will postpone this possibility to next version/iteration. (And again it is one more chip, I was not aware of, and I am happy, that I widen my knowledge about existence of this one. )

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