Hello friends, I have decided to return to electronics. Of course my focus is on AMD/Xilinx FPGA and 6502 based programming/softcore CPU. I see a few things which give me encouragement! Spartan 6 has lifespan into 2030+ and my preferred board manufacturer ExpressPCB still exists... These are my 2 common denominators for this chapter. Please do not try to convince me of better things. I need to be focused.

I have an itch to continue my 16-bit 1080p video project. It never had page flipping as I was using 1x 2Mx18 SyncRAMs and the amount of usable pins from a Spartan 6 144-pin TQFP package was not enough to accommodate 2x RAMs. Hence the need for large pin count BGA type FPGA, which I've failed at before documented here. Somewhere.

This project will start off surmounting a problem of my understanding of the board manufacturer software ability to place soldermask over a via, which are typically located in between 4 BGA pads. This has been a problem for their software in the past and the reason I had given up. I was not prepared to pay thousands for a software program to create a gerber file and also switch board manufacturers. Too much money already invested in 'the process'. Again please refrain from trying to convince me of other companies, either software or board manufacturer.

This will be approximately a 54mm x 54mm adapter board with a 484 Spartan 6 XC6SLX45T FPGA in the center. All signal header pins will be as close as possible to the FPGA. It will be a 6 layer board with the 3 voltage regulators, JTAG header and FPGA SPI FLASH and crystal oscillator all on board.

The goal here is to mount and program a 484pin BGA Spartan 6 on a board I can mount to a breadboard (push in) or for wire-wrap for testing different modules, instead of mounting alot of expensive IC's on 1 PCB board. This time I will take a modular approach.

Hello again to this great community and all comments welcome!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Oho - welcome back!

Hi Ed! Thank you, I hope you are well!

Yesterday I was able to place individual polygons over the vias on the soldermask level and after receiving a response from ExpressPCB, this is indeed the way to do it, although it seems abit clunky to me. It seems more natural to just have an option for vias to be masked or not. Oh well, problem solved.

I am debating whether to send in a 2 layer test board ($88) to make sure the process on the top level is 100%, also get the Spartan 6...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Welcome back, Sam! 484pin BGA, eh? I always did admire your fearlessness!

Will this initial module have the ability to connect with one or more other modules (or a motherboard, perhaps) and thus create a complete system? Or is this initial module merely a test vehicle for the process -- the vias etc., and the ability to program the device? (In this latter case I imagine it will only need a handful of connections to the outside world.)

Really it's the connections I'm curious about. If this initial module is intended to become part of a complete system then you'll want to consider carefully how to deal with (presumably) dozens of connections -- a challenge in regard to signal integrity issues and board space.

Congrats on the new project... Looking forward to further updates!

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Interested in your progress.

I've accidentally acquired large number of 144-pin BGA and tried to work with it on and off. The latest attempt had vias in some BGA pads. I built a 2-layer prototype, made the board thin, filled the vias with solder and tried to solder it with hot air, but wasn't very successful. Only 1 out of 4 worked. I may try again with a hot skillet.
Bill

Dr. Jeff! Hello! Thanks for your kind words, I feel very confident in mounting the 484 pin BGA for this project! You can consider this like a CPU module where all the signals come and go from, including master clocks for offboard IC's like the SyncRAM's and possibly videoDAC.
My intent is to have all 338 I/O signals from the Spartan 6 be present on a multiple headers, possibly WW. If this is not possible then just enough I/O for 2x 2Mx16 SyncRAMs and a 16 bit videoDAC, which should definitely be achieveable.
Regarding the layout, this is crucial. The way I have done it in the past is to assign the GND, 1.2V, 2.5V, 3.3V Power pins first. Then move on to the GClk and NClk pins, then general I/O. Initially I'll try 4 dedicated layers dedicated for all these Power pins. The end goal will be to sandwich the high speed clock signals between the GND and 3.3V layers and will be the closest to the S6.
I foresee placing bypass capacitors becoming a problem. I have placed them underneath the S6 before, but the concentration of pins will require extremely small bypass caps.
Finally, the voltage reg's and SPI FLASH will be onboard, but furthest away from the S6. All that will be needed is a 5VDC power source.

So right now I am really trying to find some Wire Wrap strips I could use for the S6 header I/O pins or some other nice adapters.

These are my dreams, lets see how many I can make come true!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hi plasmo, I feel your pain. I have tried a 256-pin BGA with similar success. I too have had exposed vias in between the BGA pads, i.e. no soldermask. This is probably THE biggest mistake you are making and that I had made. Also, no vias for BGA pads. This topic has come up before here. The hole will wick the solderball right off the IC.

Your goal should be:
1) ultra clean BGA pads, no solder
2) plenty of flux applied to the clean BGA pads
3) use a hotplate to heat the bottom of the circuit board evenly and maybe a little hot air on the BGA to help. You should see the BGA slump abit and maybe even self center if your lucky!

Best of luck bro! I'm a novice myself

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Certainly it would be nice to have all 338 I/O signals piped out to the headers, but have you considered the tradeoffs that'll be necessary to accomplish that? You might find the lesser goal -- ie; just enough I/O for the SyncRAMs etc -- challenging enough.

That's assuming your headers are based on .1" spacing. (Finer pitch connectors are available.) You don't want the module to get too big because the cost goes up, and also the PCB traces get longer, which in turn affects signal integrity. And speaking of signal integrity, on the headers you'll wanna intersperse plenty of ground lines between the signals lines; this is to ensure that every signal path has a nearby ground path though which the return current can flow (thus minimizing inductance).

So, for example, in a double-row header you could provide a staggered pattern with one ground pin for every 3 signal pins, raising your pin count by 33%. This 3:1 ratio would ensure that every signal pin has a ground pin no more than .1" away. (But a 2:2 or even a 1:1 ratio would be preferable.) You can think of all these extra ground pins as a partial remedy to repair some of the damage that was done to the ground plane by opting to implement the project on multiple PCBs instead of just one.

On the upside, I do understand the appeal of the modular approach. I'm sure it would be appealing to be able to reuse these very expensive FPGAs! But the savings will be offset by added design challenges and the cost of the connectors.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Hi Garth, I will read that primer before I dive in. Might be another month, finances are a little tight now and big trip coming March 1. Honeymoon in Vegas, after 21 years.

I wasn't planning on putting grounds in the headers, this will be short wire wrap pins coming off the 2" x 2" board so there won't be any lengthy travel for the signals. In the last video project I was running 5 boards on a backplane, now there I used plenty of grounds and it worked wonderfully! But in this case I don't think I need it? What do you guys think?

Maybe I'm using the word headers when I mean rows of pins. And the spacing will be .050", I have decided on that. I'm not sure if I can still use wire wrap. If not then I anticipate designing a 4 layer board for the SyncRAM's and a few other ICs.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

To answer my own question; there is no .050" wire wrap. And using .1" pitch connectors is out of the question due to the number of pins. I think I will be limited right from the beginning on the type of (.050") 1.27mm connector I can use to send signals off the FPGA board. Already spent hours searching, filtering. PITA... This is when I go straight to a manufacturer, find the part number and search Digikey or Mouser. My bet is on Mill-Max

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Interested in what others have to say. Myself, I don't think there's any yes-no answer. The only reasonable answer is more like, "if you take [no/some/many precautions] then we can cautiously predict you might have a [good/better/excellent] chance of trouble-free operation, assuming you limit your expectations to [blah blah] performance goals (ie, clock speed). Like an equation. If you alter one parameter a little bit, or a lot, then the other parameters need to be adjusted in order to balance the books.

Under "precautions," it would probably be good to rank your FPGA outputs into two classes: those that drive a clock or other noise-sensitive input, and those that drive a comparatively glitch-tolerant input such as a RAM address line. The outputs driving sensitive signals can get extra attention wrt adjacent ground pins, not to mention series termination resistors placed physically close to the FPGA. AIUI, you also can tailor the output slew rate on the FPGA pins... really there are many possible measures and tradeoffs to consider.

Honeymoon in Vegas sounds nice!

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Dr, Jeff, you said it! The logical conclusion is GND pins around all NCLK and GCLK pins, nut not necessary for regular I/O. When the time comes, I'll see if I can afford the real estate for all FPGA CLKs, the design isn't limited to ~2" x 2" (51mm x 51mm). I'm picturing maybe 3-4 rows of pins on the outer perimeter of the board. Each are .120" (3mm) wide. Starting to look like 3" x 3" board now.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Be aware you can get 1.27mm (0.050") centre header pin connectors in both surface mount and through hole. Through hole will take up less real estate than sm, oddly enough.

And of course you can get pre-wired cables to interface directly if that's the sort of thing you might need.

Neil

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x86?  We ain't got no x86.  We don't NEED no stinking x86!