I am using an external crystal oscillator for Phase 2 in (PHI2) on a WDC65C02. I previously was using the Phase 2 Out (PHI2O) for all address decoding, but after reading over the 6502 data sheet, apparently I've been doing things wrong for a very long time, and should have been using the original crystal clock source for all Phase 2 logic. Can anyone confirm this? or am I misreading something?

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

It sounds like you might be thinking of the '816, which has no φ2 output. For the 6502, you'll usually want to use the φ2 output. If you put an RC on the input to use the internal oscillator, the input is analog, as the capacitor gradually charges and discharges, without fast edges that go from deep in logic "0" territory to deep into logic "1" territory. In that case of course using the input wouldn't work at all. The timing diagrams reference everything to φ2 output.

Check out pg. 26 under Fig. 6-3 General Timing Diagram.

It says:

"Timing Notes:
1. Timing measurement points are 50% VDD.
2. PHI1O and PHI2O clock delay from PHI2 is no longer specified or tested and WDC recommends using an oscillator for
system time base and PHI2 processor input clock."

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Interesting. That is reflected also in 3.8 on page 11, but they did not increase the speed ratings from what they specified before which obviously worked. I suppose it would would be good to put in a jumper selection and try it both ways and see which way you can run it the fastest.

Do you think that this would affect the timing diags, if it were true?

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

It should, but I've seen quite a few errors in their timing diagrams over the years too, which is why I'm even thinking of using a variable delay line on my next design, and adjust it to wherever I can get the best performance out of it.

How would a variable delay line be implemented?

André

They look like an IC, but taller, like a relay that plugs into a DIP socket. See http://www.datadelay.com/ . There are different kinds to select from, ranging from rather crude, to rather cool digitally programmed ones. The data sheets are pretty clear and not complicated. I think I would chose a part with a parallel programming input that can take the programming word by DIP switches or a jumper pin header, instead of a serial input which would require the computer to be operating to change it (and changes during operation may produce a glitch that would crash the computer since we're talking about putting it in the clock line).

Edit: For a quick-n-dirty home-made one, you can also just put a tiny trimmer resistor in series with the input of a Schmitt-trigger gate. The RC formed by the trimmer and the input capacitance of the gate gives a delay that is variable as you turn the trimmer. You'll probably want a trimmer that maxes out at about 2500 ohms. The delay may not be super consistent, as the gate's input capacitance and thresholds might change depending on temperature, but it might be ok since we're not talking about an application that needs super-high accuracy, but rather one that can probably tolerate several percentage points of wandering. For example, if the adjustment range were 20ns, 5% is 1ns which should be totally fine.

In my project ( viewtopic.php?t=1370&start=165 ), I recently was having timing "issues" when trying to readback data from a flip-flop using a latch/tri-state buffer on a CPLD, that's why I started this thread, for more insight. Which, thankfully, your responses gave me some ideas.

Originally, I was using PHI2O for CPLD, and Display. All was working, except the "read" latch. Then I tried PHI2 for all devices. But I was getting some random data on my display, but it was still functioning mostly correct. Then I used PHI2O for the display (from the CPU) and PHI2 for the CPU and CPLD, now everything is working nice. Running @ 7MHz now (Display can only handle 10MHz max...)

Makes one wonder what the delay is from PHI2 to PHI2O. Not had time yet to find that out...

I will update my project thread this weekend.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Dallas Semiconductor makes an 8-bit parallel programmable delay line. They have 2 5V TTL versions which are currently available in 16-SOIC. One that has a delay from 10-74nS, and another goes from 10-138nS. Part # is DS1021S-25 & DS1021S-50. $20 each though

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

At 7MHz, I measured a delay of 50nS, from PHI2 to PHI2O. Probably different for every IC since WDC doesn't spec it, but it's a starting point...

The display ran like crap using the PHI2O for the (E) signal and all address decoding. It ran better using the PHI2O for the display and PHI2 for CPU and CPLD, and slightly even better with another 10 nS delay on the PHI2O to the display. A delay I achieved using some leftover pins of a XC9572-10 and 5 sequential AND gates. Was hoping for a 50nS delay, but seems that the software optimizes logic for speed, explaining only my 10nS delay...I'm seeing bad data maybe once every 10 seconds now.

Gonna try using the constraints in the ISE software to specify a delay for the AND gate.

- EyE

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502