Hello everyone!
Since I've had a discussion on the Forth board about adding Forth to my SBC, I was asked to introduce the machine a bit more in detail here. As I've got a lightning talk where I explain the idea of the machine in five minutes, let's start with this:
https://xayax.net/sorbus/lightning1.php.
The website is
https://xayax.net/sorbus/, the software and KiCad design files, etc is at
https://github.com/SvOlli/sorbus.
The basic idea is to combine a 6502/65C02/65816 with a clone of a Raspberry Pi Pico and just call it a computer.
And don't forget to expose the bus to allow for extensions. Since all 30 GPIO pins are required to communicate with the CPU, the USB UART is the only generic I/O left. It also provides power.
As the RP2040 of the Pico clone acts as the chipset including RAM and clock, a lot is possible. I've got three different "cores" available.
A clone of an Apple 1: well, not that much to see here. It's behaves like an Apple 1, except that the I/O is done via the USB UART. It was the first thing I implemented, since it's the most simple system I know.
Monitor Command Prompt: this one drives the CPU at a clock speed of 1 to 100.000 Hz. It is intended as a system to explain how the CPU works and to figure out how it behaves in corner cases. For me, I finally understood
why the JSR of the 6502 has to store the return address minus one on the stack. Seeing the CPU run cycle by cycle, it was rather obvious.
Sorbus Native: this is where things get interesting. This is my own design with a memory map looking like this:
- $0000-$0003: special I/O intended e.g. for an upcoming VGA card
- $0004-$CFFF: RAM
- $D000-$DEFF: I/O provided by external boards
- $DF00-$DFFF: I/O provided by main RP2040 board
- $E000-$FFFF: bank 0 (RAM, used to load CP/M 65)
- $E000-$FFFF: bank 1 (ROM, custom firmware / kernel)
- $E000-$FFFF: bank 2 (ROM, OSI BASIC)
- $FF00-$FFFF: bankswitching code, BRK handler, I/O routines, can be copied to RAM using code at $0100 after loading a bootblock.
The flash of the RP2040 is also used as a "hard disk" or "internal drive" as I call it. The interface is DMA driven (the C implementation just does a memcpy). Other neat features include a trap register one can write to to stop the CPU and come up with a "meta-menu" that allows to show the last 512 bus accesses, a poor man's logic analyser. All of this runs at ~1MHz without overclocking the RP2040.
The software side is also looking quite well right now: it's got a port of WozMon, as well as a port of the Terminal Interface Monitor of the MOS 6530-004. Furthermore there is are ports of the OSI BASIC and Tali Forth 2 included. And it also got an operating system: it's using David Given's implementation of CP/M on a 6502. Just feels like a nice fit. The kernel uses software interrupts to prove the more complex functions, like loading and saving of files, or running a few VT100 escape sequences. It's also possible to expand the software interrupt handler with own functions in RAM.
And the best part of it: in does not only invite for tinkering by the architecture, but also by the price. When ordering parts for 10 systems (gerber files are also available), the price per system is about $13. I also got a slightly cost reduced model called "Junior" which can be done for <$10 per system when building 10 systems.
If anyone is thinking about building one yourself, I'd be happy to assist. I also have enough parts here in Germany, so I can also send out PCBs or I've even got enough parts for a few kits.
Have fun,
SvOlli