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IIgs Ram Expansion slot Pinout explanation

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kktos

Post subject: IIgs Ram Expansion slot Pinout explanation

Posted: Mon Dec 11, 2023 1:55 pm

Joined: Tue Jan 12, 2021 4:57 pm
Posts: 6

Hi,
I'm wondering how the address is computed on the IIgs Ram Expansion Slot....
I see FRA0..9...
The 65C816 has a 24-bit address bus.
The 16-bit low part is like the 6502. And there are the 8-bit Program/Data Bank Register.
So why 10 bits on this slot (FRA0--9) ?
And what is the use of the A10..15 on the slot ?

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Dr Jefyll

Post subject: Re: IIgs Ram Expansion slot Pinout explanation

Posted: Mon Dec 11, 2023 4:06 pm

Joined: Fri Dec 11, 2009 3:50 pm
Posts: 3367
Location: Ontario, Canada

The "Apple iiGS Hardware Reference" will probably answer your questions. Do you have access to that PDF? (Perhaps you do, but find it hard to interpret.)

And it might be helpful if you tell us why you're asking. For example, is it mere curiosity? Are you thinking of building a card that would plug into the Ram Expansion Slot?

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

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BigDumbDinosaur

Post subject: Re: IIgs Ram Expansion slot Pinout explanation

Posted: Mon Dec 11, 2023 6:53 pm

Joined: Thu May 28, 2009 9:46 pm
Posts: 8514
Location: Midwestern USA

kktos wrote:

The 65C816 has a 24-bit address bus.

Not exactly. The 816 generates a 24-bit address (even in emulation mode), but multiplexes bits 16-23 on the data bus during Ø2 low. Typically, a transparent latch is used to capture those bits when the clock is low and then maintain them when Ø2 goes high.

Quote:

The 16-bit low part is like the 6502.

Correct. That feature is necessary to support 65C02 emulation capability.

Quote:

And there are the 8-bit Program/Data Bank Register.

From a hardware decoding standpoint, the contents of DB and PB are not relevant unless the glue logic monitors the state of VDA and VPA. If that is the case, then the glue logic will “know” when a cycle is an opcode fetch (VDA && VPA is true), operand fetch (!VDA && VPA is true) or data fetch/store (VDA && !VPA is true). From that, it can be inferred if PB is influencing the effective address, since it is PB that determines bits 16-23 during opcode and operand fetches. However, while VDA && !VPA tells you that a data fetch/store is occurring, it doesn’t tell you if bits 16-23 reflect what is in DB. This is because an effective address generated by the absolute-long or indirect-long addressing modes does not get bits 16-23 from DB.

Quote:

So why 10 bits on this slot (FRA0--9) ?
And what is the use of the A10..15 on the slot ?

The answer to that is likely in the manual mentioned by Jeff.

_________________
x86? We ain't got no x86. We don't NEED no stinking x86!

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kktos

Post subject: Re: IIgs Ram Expansion slot Pinout explanation

Posted: Mon Dec 11, 2023 7:09 pm

Joined: Tue Jan 12, 2021 4:57 pm
Posts: 6

Thanx a lot guys.

Quote:

The "Apple iiGS Hardware Reference" will probably answer your questions.

Oh yeah, the hardware ref.... damned.. I used to have this book....
Get rid of almost everything some 23 years ago....
yep, stupid.

Quote:

Do you have access to that PDF?

just downloaded it

Perfect.

Quote:

is it mere curiosity?

Right now, yes, it is.
still grooming

Quote:

BigDumbDinosaur: Not exactly.

I'm a software engineer, hence the inacurate HW description.
But yop, you're definitively right. And that's part of the difficulties to deal with the 65C816.
Timing is the essence.

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