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PostPosted: Mon Dec 04, 2023 12:58 pm 
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10a) register 4 //vertical total
10b) register 6 //vertical displayed
10c) register 7 //vertical SYNC position

Attachment:
r6545r1_10def_reg4_reg6_reg7.png
r6545r1_10def_reg4_reg6_reg7.png [ 136.38 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_10d_latch.png
si_r6545r1_10d_latch.png [ 20.72 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_10def_inverters.png
si_r6545r1_10def_inverters.png [ 13.07 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_10def_reg4_reg6_reg7.png
si_r6545r1_10def_reg4_reg6_reg7.png [ 31.92 KiB | Viewed 5816 times ]


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PostPosted: Mon Dec 04, 2023 12:59 pm 
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11) HCC counter plus logic

Counts the horizontal characters.

Attachment:
r6545r1_11abc_hcc_counter_plus_logic.png
r6545r1_11abc_hcc_counter_plus_logic.png [ 112.05 KiB | Viewed 5816 times ]


Attachment:
si_6545r1_11a_hcc0_counter.png
si_6545r1_11a_hcc0_counter.png [ 20.63 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_11b_hcc_carry.png
si_r6545r1_11b_hcc_carry.png [ 31.89 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_11c_hcc_clear.png
si_r6545r1_11c_hcc_clear.png [ 21.12 KiB | Viewed 5816 times ]


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PostPosted: Mon Dec 04, 2023 1:08 pm 
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12) MA counter

(display) Memory address counter,
and it's a lot of stuff.

;---

Attachment:
r6545r1_12abcd_mal_counter_plus_logic.png
r6545r1_12abcd_mal_counter_plus_logic.png [ 149.09 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_12a_ma0_counter.png
si_r6545r1_12a_ma0_counter.png [ 34.44 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_12b_mal_carry.png
si_r6545r1_12b_mal_carry.png [ 31.73 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_12c_mal_inv_east.png
si_r6545r1_12c_mal_inv_east.png [ 14.99 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_12d_mal_inv_west.png
si_r6545r1_12d_mal_inv_west.png [ 26.88 KiB | Viewed 5816 times ]

;---

Attachment:
r6545r1_12ef_mah_counter_plus_logic.png
r6545r1_12ef_mah_counter_plus_logic.png [ 125.97 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_12e_ma8_counter.png
si_r6545r1_12e_ma8_counter.png [ 31.55 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_12f_mah_carry.png
si_r6545r1_12f_mah_carry.png [ 21.81 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_12e_mah_inverters.png
si_r6545r1_12e_mah_inverters.png [ 21.05 KiB | Viewed 5816 times ]

;---

Attachment:
r6545r1_12g_mah_ld.png
r6545r1_12g_mah_ld.png [ 109.02 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_12g_mah_ld.png
si_r6545r1_12g_mah_ld.png [ 61.22 KiB | Viewed 5816 times ]

;---

Attachment:
r6545r1_12h_mah_cen.png
r6545r1_12h_mah_cen.png [ 47.02 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_12h_mah_cen.png
si_r6545r1_12h_mah_cen.png [ 38.15 KiB | Viewed 5816 times ]


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PostPosted: Mon Dec 04, 2023 1:11 pm 
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13a) register 17 //light pen L
13b) register 15 //cursor position L
13c) register 16 //light pen H
13d) register 14 //cursor position H

Attachment:
r6545r1_13ab_reg17_reg15.png
r6545r1_13ab_reg17_reg15.png [ 87.08 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_13ab_inv_east.png
si_r6545r1_13ab_inv_east.png [ 12.08 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_13ab_reg17_reg15.png
si_r6545r1_13ab_reg17_reg15.png [ 22.72 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_13b_reg15_nand.png
si_r6545r1_13b_reg15_nand.png [ 13.37 KiB | Viewed 5816 times ]

;---
Attachment:
r6545r1_13cd_reg16_reg14.png
r6545r1_13cd_reg16_reg14.png [ 51 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_13cd_inverters.png
si_r6545r1_13cd_inverters.png [ 14.11 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_13cd_reg16_reg14.png
si_r6545r1_13cd_reg16_reg14.png [ 23.79 KiB | Viewed 5816 times ]


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PostPosted: Mon Dec 04, 2023 1:12 pm 
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14) CBC counter plus logic

Cursor blink counter.
This is, what makes the cursor blink.

Attachment:
r6545r1_14ab_cbc_counter_plus_logic.png
r6545r1_14ab_cbc_counter_plus_logic.png [ 145.35 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_14a_cbc0.png
si_r6545r1_14a_cbc0.png [ 19.27 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_14b_cbc_logic.png
si_r6545r1_14b_cbc_logic.png [ 63.28 KiB | Viewed 5816 times ]


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PostPosted: Mon Dec 04, 2023 1:15 pm 
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15a) register 10 //cursor end
15b) register 11 //cursor start
15c) register 9 //scan lines

Attachment:
r6545r1_15abc_reg10_reg11_reg9.png
r6545r1_15abc_reg10_reg11_reg9.png [ 150.41 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_15abc_reg10_reg11_reg9.png
si_r6545r1_15abc_reg10_reg11_reg9.png [ 56.01 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_15abc_inverters.png
si_r6545r1_15abc_inverters.png [ 13.35 KiB | Viewed 5816 times ]

;---

15d) RA counter //raster address

Attachment:
r6545r1_15d_ra_counter.png
r6545r1_15d_ra_counter.png [ 254.81 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_15d_ra_counter.png
si_r6545r1_15d_ra_counter.png [ 93.73 KiB | Viewed 5816 times ]


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PostPosted: Mon Dec 04, 2023 1:17 pm 
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16) RA logic

Big blob of conventional logic, tied to the RA counter.

It turned out that most of it is for turning the cursor on/off
in a specific raster line.

And I have to say that the interlaced mode sure adds a lot to the complexity.

Attachment:
r6545r1_16_ra_logic_part2.png
r6545r1_16_ra_logic_part2.png [ 334.55 KiB | Viewed 5816 times ]

Attachment:
r6545r1_16_ra_logic_part1.png
r6545r1_16_ra_logic_part1.png [ 257.46 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_16_ra_logic.png
si_r6545r1_16_ra_logic.png [ 224.12 KiB | Viewed 5816 times ]


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PostPosted: Mon Dec 04, 2023 1:19 pm 
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17) VRC counter

Counts the horizontal characters. //I think.
//Hey, I had to give that thing a name...

Attachment:
r6545r1_17abc_vrc_counter_plus_logic.png
r6545r1_17abc_vrc_counter_plus_logic.png [ 125.02 KiB | Viewed 5816 times ]

Attachment:
r6545r1_17d_vrc_cen.png
r6545r1_17d_vrc_cen.png [ 85.94 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_17a_vrc0_counter.png
si_r6545r1_17a_vrc0_counter.png [ 15.96 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_17b_vrc_varry.png
si_r6545r1_17b_vrc_varry.png [ 27.21 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_17c_vrc_clear.png
si_r6545r1_17c_vrc_clear.png [ 23.5 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_17d_vrc_cen.png
si_r6545r1_17d_vrc_cen.png [ 51.02 KiB | Viewed 5816 times ]


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PostPosted: Mon Dec 04, 2023 1:23 pm 
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18) VAC counter

For vertical total scan line adjust.

Attachment:
r6545r1_18a_reg5.png
r6545r1_18a_reg5.png [ 42.65 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_18a_reg5.png
si_r6545r1_18a_reg5.png [ 23.6 KiB | Viewed 5816 times ]

;---

Attachment:
r6545r1_18bc_vac_counter_plus_logic.png
r6545r1_18bc_vac_counter_plus_logic.png [ 69.36 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_18b_vac4_vac3.png
si_r6545r1_18b_vac4_vac3.png [ 21.73 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_18c_vac_carry.png
si_r6545r1_18c_vac_carry.png [ 24.41 KiB | Viewed 5816 times ]

;---

Attachment:
r6545r1_18d_vac_counter_control.png
r6545r1_18d_vac_counter_control.png [ 117.23 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_18d_vac_control.png
si_r6545r1_18d_vac_control.png [ 67.22 KiB | Viewed 5816 times ]

Note that Schmitt Trigger in 18d),
which implicates that the designer expected to have some spikes
in the output signal from the register 0 comparator:

Attachment:
si_r6545r1_18d_vac_control_schmitt.png
si_r6545r1_18d_vac_control_schmitt.png [ 68.24 KiB | Viewed 5816 times ]


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PostPosted: Mon Dec 04, 2023 1:29 pm 
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19a) register 8, Bit 7..6 //mode control
19b) register 3, Bit 7..6 //HSYNC, VSYNC widths

//To me it feels like the chip designers ran a bit out of space in 19),
//and tried to squeeze all that stuff in a limited amount of space.

Attachment:
r6545r1_19ab_reg8_76_reg3_76.png
r6545r1_19ab_reg8_76_reg3_76.png [ 64.35 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_19ab_reg8_76_reg3_76.png
si_r6545r1_19ab_reg8_76_reg3_76.png [ 44.16 KiB | Viewed 5816 times ]

;---

19c) register 8, Bit 5..0 //mode control
19d) register 3, Bit 5..0 //HSYNC, VSYNC widths

Attachment:
r6545r1_19cd_reg8_50_reg3_50.png
r6545r1_19cd_reg8_50_reg3_50.png [ 85.78 KiB | Viewed 5816 times ]


Attachment:
si_r6545r1_19cd_output_inverters.png
si_r6545r1_19cd_output_inverters.png [ 18.41 KiB | Viewed 5816 times ]

Attachment:
si_r6545r1_19cd_reg8_50_reg3_50.png
si_r6545r1_19cd_reg8_50_reg3_50.png [ 38.83 KiB | Viewed 5816 times ]


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PostPosted: Mon Dec 04, 2023 1:34 pm 
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19ef) HSW counter plus logic //width of the horizontal SYNC pulse.

Attachment:
r6545r1_19ef_hsw_counter_plus_logic.png
r6545r1_19ef_hsw_counter_plus_logic.png [ 64.73 KiB | Viewed 5815 times ]


Attachment:
si_r6545r1_19e_hsw01_counter.png
si_r6545r1_19e_hsw01_counter.png [ 24.56 KiB | Viewed 5815 times ]

Attachment:
si_r6545r1_19f_hsw_carry.png
si_r6545r1_19f_hsw_carry.png [ 25.51 KiB | Viewed 5815 times ]

;---

19g) VSW counter plus logic //width of the vertical SYNC pulse.

Attachment:
r6545r1_19g_vsw_counter_plus_logic.png
r6545r1_19g_vsw_counter_plus_logic.png [ 142.28 KiB | Viewed 5815 times ]


Attachment:
si_r6545r1_19g_vsw.png
si_r6545r1_19g_vsw.png [ 63.82 KiB | Viewed 5815 times ]

;---

19h) HSW counter control

Attachment:
r6545r1_19h_hsw_counter_control.png
r6545r1_19h_hsw_counter_control.png [ 116.82 KiB | Viewed 5815 times ]


Attachment:
si_r6545r1_19h_hsw_counter_control.png
si_r6545r1_19h_hsw_counter_control.png [ 75.2 KiB | Viewed 5815 times ]

Note that low pass filter in 19h),
which is built from a FET resistor and the gate capacitance of an inverter.
The designers obviously expected to have some spikes
in the output of the register 2 comparator.

Attachment:
si_r6545r1_19h_hsw_counter_control_lowpass.png
si_r6545r1_19h_hsw_counter_control_lowpass.png [ 78.45 KiB | Viewed 5815 times ]


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PostPosted: Mon Dec 04, 2023 1:37 pm 
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20) status register

Attachment:
r6545r1_20_status_register.png
r6545r1_20_status_register.png [ 79.96 KiB | Viewed 5815 times ]


Attachment:
si_r6545r1_20_status_register.png
si_r6545r1_20_status_register.png [ 103.3 KiB | Viewed 5815 times ]


Because RES isn't your average reset signal,
the designers had added some power_on reset circuitry
for clearing Bits in the status register.

Attachment:
si_r6545r1_20_por.png
si_r6545r1_20_por.png [ 14.57 KiB | Viewed 5815 times ]


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PostPosted: Mon Dec 04, 2023 1:38 pm 
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21) register 31 read write

Mostly some shenanigans for incrementing the address pointer
when it comes to register 31 reads/writes.

//Note, that the Rockwell R6545 keeps the drivers to the
//D0..D7 external data bus in high impenance
//for register 31 reads.

Attachment:
r6545r1_21_reg31_read_write.png
r6545r1_21_reg31_read_write.png [ 207.7 KiB | Viewed 5815 times ]


Attachment:
si_r6545r1_21_reg31_read_write.png
si_r6545r1_21_reg31_read_write.png [ 74.98 KiB | Viewed 5815 times ]


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PostPosted: Mon Dec 04, 2023 1:38 pm 
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And that's all.


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PostPosted: Sun Dec 10, 2023 3:32 am 
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Many thanks for that great amount of work! I'll certainly have a deeper look!

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/


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