The W65C256 Revisited

[Jmstein7]

Hi, all! A few years ago, I picked up the Western Design Center W65C265 boards - the W65C265SBX and W65C265QBX. Unfortunately, once I had them in hand, it was apparent that WDC had hobbled these boards with slow clock speeds, inaccessible ports, and a labyrinthine internal ROM. It was a shame, because, despite its quirks, the W65C265 itself is quite capable. It is a 65C816 with demultiplexed address lines, capable of good 65C816 performance at 8mhz.

Moreover, it has very handy peripherals built in - which can be harnessed if you figure out how to program the quirks away. For example, on an 8MHZ clock, it's internal UARTs can rev up to 0.5MHZ, without the annoyance of the hardware handshakes, and work-arounds, that come with the 65C51 - and none of the hardware bugs!

The documentation is very cryptic, so it took a lot of work to figure it out. Along with some help from David Gray of the WDC, who was kind enough to lend a hand, and his time, and help me understand this chip. Subsequently, I built my own board and had it made, which was my first (and only) PCB. It has every pin exposed for expansion, including its BBC Tube-like Parallel Interface Bus, which allows the user to connect peripherals like coprocessors. It has built-in message passing!

So, here is what I have, below. I hope you guys can provide some feedback, ideas, &c. And, yes, I know my PCB is less-than-optimized!

[Proxy]

oooh, fancy!
don't mind me using this as a base for my own '265 board.
one of my ideas is to (maybe) completely ignore the built-in CS outputs and only use external decoding logic and the BA pin (Bus Available) to handle external Memory and IO devices. just because i'd like to see if that would improve performance, or if the built-in CS outputs are faster than an external CPLD when overclocking.
speaking of which, i asked it in the other thread since you mentioned running this chip at (official) maximum speed, but you didn't give an answer. so have you tried overclocking it, even just a little like 10MHz?

on a side note, could you do some measurements on various signals using an oscilloscope (if you have one) to see how long the Address lines, Control signals like RW, BA, CS0-7, etc take relative to the PHI2 clock input. as the official datasheet is WDC made, and therefore likely very pessimistic with it's timings.

and finally, if you would be so nice to post about any facts or things you learned about this chip that either weren't very clear or not included in the datasheet. or just any general info you know.
some example: how do you get it to boot off an external ROM, why FCLK needs to be >4x the speed of CLK, and what happens when that is not the case?

[Jmstein7]

Proxy wrote:

oooh, fancy!
don't mind me using this as a base for my own '265 board.
one of my ideas is to (maybe) completely ignore the built-in CS outputs and only use external decoding logic and the BA pin (Bus Available) to handle external Memory and IO devices. just because i'd like to see if that would improve performance, or if the built-in CS outputs are faster than an external CPLD when overclocking.
speaking of which, i asked it in the other thread since you mentioned running this chip at (official) maximum speed, but you didn't give an answer. so have you tried overclocking it, even just a little like 10MHz?

on a side note, could you do some measurements on various signals using an oscilloscope (if you have one) to see how long the Address lines, Control signals like RW, BA, CS0-7, etc take relative to the PHI2 clock input. as the official datasheet is WDC made, and therefore likely very pessimistic with it's timings.

and finally, if you would be so nice to post about any facts or things you learned about this chip that either weren't very clear or not included in the datasheet. or just any general info you know.
some example: how do you get it to boot off an external ROM, why FCLK needs to be >4x the speed of CLK, and what happens when that is not the case?

Great questions! On the overclocking, the problem is that you have to use one six specific frequencies to make everything onboard the chip work right (although one of the "approved" frequencies - 6.1440MHz - didn't seem to work). The frequencies are 1.8432MHz, 2.4576MHz, 3.6864MHz, 4.9152MHz, 6.1440MHz, and 8mhz. So, no, I didn't overclock. I was just happy to get it working at its rated max.

I wish I had an oscilloscope, though I do have a decent selection of FPGAs that I suppose I could use as a logic analyzer. Oscilloscope - the one critical tool I lack.

As to booting of an external ROM, you need to know the internal ROM boot sequence. All that info actually resides here:
https://www.wdc65xx.com/wdc/documentation/265monrom.pdf

You can see it reflected in the (WIP) external ROM monitor I included, above.

Thanks for the questions! I have to think about the rest.

Jonathan

[Proxy]

why those specific clock speeds though? is it just related to the UARTs and the predefined timer values in the internal ROM? and in that case why would that matter when you boot off an external ROM anyways and can program the timers to whatever value you want? or use an external UART alltogether, personally i'd be using my beloved FT240X.

either way thanks for the document, i'll be looking through it for any info i might need!

[Jmstein7]

Proxy wrote:

why those specific clock speeds though? is it just related to the UARTs and the predefined timer values in the internal ROM? and in that case why would that matter when you boot off an external ROM anyways and can program the timers to whatever value you want? or use an external UART alltogether, personally i'd be using my beloved FT240X.

either way thanks for the document, i'll be looking through it for any info i might need!

I don't disagree. Give it a shot. Now, I'm curious

It's a shame that one has to dig so deep to even make the chip useful. But, once you do, it's powerful (for what it is).

Jonathan

[Jmstein7]

Proxy wrote:

either way thanks for the document, i'll be looking through it for any info i might need!

PS As an experiment, maybe tonight, I will try connecting a Transputer, an INMOS T805-25, to the W65C265's PIB via a Transputer C011 serial link. I wonder if I can get it to boot? At a minimum, it would make a cool FPU

Jonathan

[gfoot]

Thanks for the investigation, it is interesting to see what you and Gordon find with these microcontroller variants.

I am curious why you put two 65C51s on the board? Was that just in case you couldn't get the built-in UARTs working?

[Jmstein7]

gfoot wrote:

I am curious why you put two 65C51s on the board? Was that just in case you couldn't get the built-in UARTs working?

Yeah, sort of. One is sort of an escape hatch, or back door, should I have trouble with the onboard peripherals. Also there just for general use.

The other was meant to interface with a 4D Systems uVGA-III, along with the 65C22. However, it didn't quite work out the way I hoped. I was hoping to find a way to control the uVGA-III with the parallel bus. I had a whole library ready (https://github.com/jmstein7/uVGA_65C02_Serial_Library), but it was just too slow. And not as feature rich as I hoped. Oh, well. In my next revision, if I get to it, that will change.

Jonathan

[BigDumbDinosaur]

Using XMODEM on a hard-wired data link makes no sense to me.  TIA-232 over a couple of feet of UTP cable is about as reliable a transfer medium as anything.

I have a serial link from my office software development server into my shop, with a total of 74 feet (~22.5 meters) of UTP in the run.  It runs error-free at 115.2 Kbps with CTS/RTS flow-control.  If I’ve got a POC unit on the bench in the shop, I can send data to it using Motorola S-records without error.  No antique error-correcting protocol is needed.