10a) register 4 //vertical total
10b) register 6 //vertical displayed
10c) register 7 //vertical SYNC position

11) HCC counter plus logic

Counts the horizontal characters.

12) MA counter

(display) Memory address counter,
and it's a lot of stuff.

;---







;---






;---




;---

13a) register 17 //light pen L
13b) register 15 //cursor position L
13c) register 16 //light pen H
13d) register 14 //cursor position H






;---

14) CBC counter plus logic

Cursor blink counter.
This is, what makes the cursor blink.

15a) register 10 //cursor end
15b) register 11 //cursor start
15c) register 9 //scan lines





;---

15d) RA counter //raster address

16) RA logic

Big blob of conventional logic, tied to the RA counter.

It turned out that most of it is for turning the cursor on/off
in a specific raster line.

And I have to say that the interlaced mode sure adds a lot to the complexity.

17) VRC counter

Counts the horizontal characters. //I think.
//Hey, I had to give that thing a name...

18) VAC counter

For vertical total scan line adjust.




;---





;---




Note that Schmitt Trigger in 18d),
which implicates that the designer expected to have some spikes
in the output signal from the register 0 comparator:

19a) register 8, Bit 7..6 //mode control
19b) register 3, Bit 7..6 //HSYNC, VSYNC widths

//To me it feels like the chip designers ran a bit out of space in 19),
//and tried to squeeze all that stuff in a limited amount of space.




;---

19c) register 8, Bit 5..0 //mode control
19d) register 3, Bit 5..0 //HSYNC, VSYNC widths

19ef) HSW counter plus logic //width of the horizontal SYNC pulse.





;---

19g) VSW counter plus logic //width of the vertical SYNC pulse.




;---

19h) HSW counter control




Note that low pass filter in 19h),
which is built from a FET resistor and the gate capacitance of an inverter.
The designers obviously expected to have some spikes
in the output of the register 2 comparator.

20) status register





Because RES isn't your average reset signal,
the designers had added some power_on reset circuitry
for clearing Bits in the status register.

21) register 31 read write

Mostly some shenanigans for incrementing the address pointer
when it comes to register 31 reads/writes.

//Note, that the Rockwell R6545 keeps the drivers to the
//D0..D7 external data bus in high impenance
//for register 31 reads.

And that's all.

Many thanks for that great amount of work! I'll certainly have a deeper look!

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/