Joined: Thu May 28, 2009 9:46 pm
Posts: 8504
Location: Midwestern USA
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BigDumbDinosaur wrote: All parts have arrived. Now, all I gotta do is find some time to build and test this contraption. Maybe tonight after the 10 o’clock news...  The test rig has been built and tested. For some completely unfathomable reason, it functions exactly as intended.  First, here is a photo I took of the unit after hooking it up to the logic analyzer:
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File comment: Test Rig Connected to Logic Analyzer
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When the push button at the left end of the unit is pressed, a 1 µsec pulse will be generated to start the wait-state cycle. I shamelessly “borrowed” the pulse-generator circuit from Garth’s clock page on his website.  For the record, the observed pulse duration is 1.036 µsecs.
The observant will notice that I haven’t installed the output clamping diodes. For some reason, I thought I had some BAT85s in my parts pile, but that wasn’t the case. All I had were some SD103s, which with a 10ns TRR, aren’t fast enough. I’ll get some BAT85s with the next parts order and will subsequently post before-and-after photos of what the clock outputs look like on the scope.
I did scope the clock outputs to verify amplitude and waveform. There’s a tad bit of ringing, which is to be expected with the extremely fast edges emitted by 74AC devices. The ringing is more pronounced on the upstream side of the resistor network that drives the outputs, which tells me series resistance is helping. It’ll be interesting to see what the clamping diodes do.
Meanwhile, I ran some logic analyzer tests to see if theory and practice were approximately the same. See here for the test rig’s schematic. Signals being observed in the tests are:
- Global clock, aka GCLK. All timing is referenced to GCLK, which runs at the same speed as the oscillator and is never stretched.
Something worth noting: in this circuit, clock symmetry is exactly the same as the oscillator’s. Typically, 100 PPM can oscillators have a duty cycle rating that ranges from 47-53 to 53-47. A system clocked by an asymmetric oscillator and running close to the limits of the MPU can fall victim to difficult-to-diagnose timing violations. I’ll talk a bit more about this later on.
- Timing clock, aka TCLK. TCLK is the clock source for the 74AC109 timing flip-flop that controls stretching, and is derived from GCLK. As I surmised that there might be some benefit to having TCLK slightly lag GCLK, I rigged up a jumper block on the board so I could directly drive TCLK from GCLK, or add some lag to TCLK by inserting one or two gates into the signal path.
- Ø1 & Ø2. Ø1 and Ø2 are stretched whenever a wait-state is needed. In a 65C02 system, Ø1 is unlikely to be needed, but would be useful with a 65C816 to gate the bank latch and data bus transceiver.
- Wait-state enable, aka /WSE. In the test rig, /WSE is driven by a Schmitt inverter that is part of the pulse generator circuit. In a practical application, the glue logic would drive this signal low when a wait-state is required.
- Stop, aka STP. This signal is the /Q output of the AC109 timing flop—STP is actually high-true. I sampled it with the logic analyzer to gain a feel for how long it would take the flop to “wake up” after /WSE was asserted.
Before continuing, I must note that the logic analyzer has a 2ns resolution, which means some timing results need to be taken with a grain of salt, especially at the higher clock rates. In an effort to make things look as realistic as possible, I set the logic analyzer’s notion of where a logic transition occurs at VCC × 0.5, VCC being 5 volts (measured voltage at the input connector was 5.03). The set logic transition point definitely affects how the logic analyzer fudges some timing numbers.
Here are the test results.
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File comment: Running @ 1 MHz, 1 Wait-State
wait_state_v2_01mhz_1ws.gif [ 48.97 KiB | Viewed 2248 times ]
Above is a run with a 1 MHz oscillator in the test rig, and the rig configured to generate one wait-state. It can be seen that Ø1 and Ø2 are stretched by one extra GCLK cycle. It’s not readily observable in this run or the next one, but there is a slight lag between GCLK and TCLK.
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File comment: Running @ 1 MHz, 2 Wait-States
wait_state_v2_01mhz_2ws.gif [ 55.18 KiB | Viewed 2248 times ]
Above is another run with the 1 MHz oscillator, but with the rig configured to generate two wait-states.
The purpose of this run and the previous one was to prove that the circuit functions as intended. In a practical sense, a 1 MHz system should not ever need wait-stating, given the speeds of modern hardware. Needless to say, two wait-states at 1 MHz would be gross overkill with just about any hardware we might ever use, even 1970s-vintage parts. However, as will soon be seen, this circuit can be run at much higher speeds, at which time, two wait-states might come in handy.
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File comment: Running @ 20 MHz, 1 Wait-State
wait_state_v2_20mhz.gif [ 49.79 KiB | Viewed 2248 times ]
Above is a run at 20 MHz, with the rig configured to generate one wait-state. There is plenty of timing head room available. The lag between GCLK and TCLK is clearly visible.
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File comment: Running @ 40 MHz, 1 Wait-State
wait_state_v2_40mhz.gif [ 53.79 KiB | Viewed 2248 times ]
Above is a run at 40 MHz, also with the rig configured to generate one wait-state. There is still some timing head room available and, in fact, the numbers suggest the circuit would be reliable to at least 60 MHz. Fudging effects by the logic analyzer are obvious, in that it appears Ø1 and Ø2 are rising and falling at different times. Observation with the scope (275 MHz) indicates that the two signals are in step.
Some notes:
- In all of the above runs, TCLK is configured to maximally lag GCLK—there are two gate delays between the latter and the former. However, the total lag is small, as it turns out the OR gates through which TCLK is derived are substantially faster than the data sheet lets on. Obviously, that lag could vary with different parts, and definitely would be greater at a lower VCC, but I suspect modern iterations of 74AC logic have gotten substantially faster with improved wafer fabricating processes.
- Observed clock symmetry varied from one oscillator to another. However, that observation needs to be considered against fudging effects by the logic analyzer. Fudging is especially noticeable when an interval being observed is not evenly divisible by 2. At maximum resolution, the logic analyzer will round things to the nearest 2 ns, which may cause symmetric signals to appear asymmetric. For example, the clock phase period at 40 MHz is 12.5 ns. The limits of the logic analyzer’s resolution would represent that as 12 ns, causing the 40 MHz clock to “look funny.”
- As the AC109 timing flop is clocked at the same frequency as GCLK and the unstretched Ø1 and Ø2 clocks, gating the flop’s /K input by /WSE is not nearly as timing-critical as is the case with the circuit I presented much earlier in this topic. In that circuit, the reference clock is the oscillator, which runs at twice the speed of GCLK, making the available timing window a lot smaller. In this circuit, as long as /WSE goes low at least TSU nanosecs (~5 ns minimum with a 74AC109 at 5 volts) before the rise of TCLK, the circuit should be reliable.
- A solution to dealing with oscillator asymmetry in a “ragged-edge” application would be to pass the oscillator’s output through a flop. That flop would solely function to produce a symmetric clock to the gates that make up the rest of this circuit. Obviously, the oscillator would have to run at twice the desired clock rate.
- There may be some other permutations of this circuit that I may explore. They have yet to gel in my mind, likely due to me being a old curmudgeon whose brain is slowly wasting away.
_________________ x86? We ain't got no x86. We don't NEED no stinking x86!
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So I went with DIP parts and 0.100" (2.54mm) hole spacing.
