Hi guys,

I am presently playing with native mode on a W65C816, but am soon running in to issues with 16 bit numbers. I am using the CA65 compiler.

It throws the following error, so it seems the compiler still wants an 8 bit number.


Here's the snippet of code I am focusing on, with the last line being the offending one.


The command to compile is being instructed to build for the 65816, and the build is indeed happy with the XCE and REP commands.

Any idea's of what I am missing would be greatly appreciated.

Seems to be a compiler issue, as the following works at storing a 16 bit value to RAM perfectly.

Hmmm. Looks like you have to pepper .A8, .A16, etc.. throughout your code when you switch between 8 & 16 bit address mode.

Oh well. It works now I guess.

I think that's normal and unavoidable: the assembler needs to know the machine mode. Bear in mind the place(s) where the machine mode is changed might be quite distant from the place(s) where the sizes of registers is important.

yea that's just how ca65 works, it doesn't automaitcally track the m/x flags, Direct Page, Data Bank, or Program Bank values. (which would be a nice to have feature, but it seems pretty complicated to implement, as you basically need to track program execution while assembling)

you need to use the directives to tell it what the state the m/x flags are. it's not as annoying as it sounds since i highly recommend using macros to set the Register widths anyways instead of using raw REP/SEP instructions

here are the ones i use:



though sometimes it's still necessary to directly place the .Ax and .Ix directives, for example i recommend placing them at the start of each function so that the assembler works correctly in case you place some other function above it that uses different register widths.

also the assembler is pretty stingy with operand sizes, since there are no directives to tell it the current Data Bank or Direct Page you have to manually cut addresses down to the right size if you want it to use absolute or direct page addressing modes.
for example:



you can check out ca65's docs on more of these pseudo functions: https://www.cc65.org/doc/ca65-10.html

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What's an additional VIA among friends, anyhow?

on a similar note, Calypsi C's assembler also doesn't require size directives, though it's the opposite of C32 because it defaults to 8-bits and you specify 16-bit immediates by using ##.

so for example "LDA #$10" assembles to "A9 10" while "LDA ##$10" assembles to "A9 10 00".

plus you get a functional C compiler with it so that's nice.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

true i guess, but when you make mistakes like that it shouldn't be that difficult to spot if you use comments and such to note what registers should be what width every now and then.


oops, forgot that exists. but also note that it doesn't make the assembler follow program flow, so even when you're not using any PHP/PLP instructions it could still easily be wrong if you purely rely on .smart due to the order in which the assembler does it's work.


now i'm interested, why not? i'd say a mode is defined as something that changes the way some subset of instructions are fetched and/or executed. all of those line up with the register widths as they effect almost every memory accessing instruction.

the 6502/65C02 already has 2 modes, the D flag for either Binary or Decimal Addition/Subtraction. it's even called "Decimal Mode".
so even when you exclude the register widths, the 65816 would have atleast 4 operating modes: Emulation Binary, Emulation Decimal, Native Binary, and Native Decimal.
Bruce Clark's page on the 65816 includes the register widths as modes, so he's saying the CPU has a total of 10 different modes: http://www.6502.org/tutorials/65c816opcodes.html#6.10.3

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

But changing the width does change how the instructions behave, including the clock cycles required to achieve the task. And the fact that you have to switch processor flags along with it.

If they had used a different opcode for the 8 and 16 bit operations, then I’d agree that there is no ‘mode’ change. But the fact they used the same opcodes and you have to prewarn the CPU what types you are dealing with certainly seems like a mode change to me.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

WDC appear to agree with you. BDD is the only person I've noticed expressing an opinion in the opposite direction.

65816 datasheet, section 2.8:

They use the same language for E.

I would dispute that register widths have no effect on how instructions behave. Some instructions change length. Most of them change behaviour: ADC is either doing an 8 bit or 16 bit add, one or two bytes in memory will be written, indexed addressing modes are using either 8 bits or 16 bits of the index. It's a bigger change than decimal mode, and we've been calling that decimal mode forever.

I suspect the confusion comes from trying to see the whole processor being in a single mode at a time. That's not how it works, and it's not a helpful way to look at it. The processor is made (conceptually, at least) from a number of sub-systems, and some of these have mode flags that control their behaviour. They are mostly independent choices affecting single sub-systems, but there is some overlap in the case of E (which is an ugly mess).