RDY vs CLOCK STRETCHING. Includes a few very simple circuits

[Dr Jefyll]

Just a quick note to mention I've fleshed out my clock-stretcher post upthread with additional images and better description of the actual results.

-- Jeff

[gfoot]

Dr Jefyll wrote:

It's a little odd how I've used the shift register, so allow me to point out that it produces two different time delays -- one of the 2X clock periods, or eight -- according to the direction it's shifting... and the direction depends on /STRCH, the circuit's stretch-request input. Note that the shift-reg always gets cleared at the time Phi2 rises; in fact, that's what causes Phi2 to rise.

It's a really nice idea, shifting in different directions for the different periods. It seems very flexible for exactly how slow the stretched clock is, with a potentially easy way to tune that (see below).

Dr Jefyll wrote:

The main circuit operates as intended, but the optional J-K flipflop isn't working properly yet. In future, it will generate a uniform, full speed, non-stretched Phi2 to protect the time-keeping if there's a full-speed VIA in the system.

I think I see the problem with the JK flipflop - I'm inferring that you want it to toggle when CPU PHI2 was previously high, and get cleared when PHI2 was previously low, then tap the VIA PHI2 from its inverted output. (I think there's an extra inverter there that's not needed, probably just a mistake in the schematic.)

This relies on CPU PHI2 only ever being low for one 2X_CK cycle at a time, and always having an odd-length high period. That's not a limitation of the circuit - it's necessary if we are ever going to have CPU PHI2 match up with 2X_CK, as otherwise after a slow cycle CPU PHI2 will be low when VIA PHI2 is already high. However, from the scope trace it looks like you're currently getting an even-length high period, so that's always going to go out of phase with VIA PHI2 and then cause VIA_PHI2 to be delayed to bring itself back in sync.

I think that instead of using inverted IO0 to drive CPU PHI2, you could use the NOR of IO0 and IO1. This would reduce the length of the low phase by one 2X_CK cycle, to 7 rather than 8. And also allow the user to connect to IO3 or IO5 instead of IO1 to get less stretched signals (5 cycles and 3 cycles respectively).