Proxy wrote:
that HD63484 ACRTC is looking pretty damn good. Utsource has lots of them in stock it seems, at pretty good prices too.
plus you can apparently chain them together... though i still don't fully understand how that would work in terms of VRAM and accessing it.
But besides that, i'm a bit confused about it's operating speed.
for example if you were to try and generate 640x480 @ 8bpp, each memory access would grab 2 bits worth of data (16-bit VRAM bus), and it takes 2 cycles per memory access. that works out to 1 pixel per cycle, which at a pixel clock of 25MHz would mean the chip would need to run at 25MHz as well.
that's a bit of an issue considering that it's rated for at most 8MHz... and it boasts resolutions 4096x4096 @ 1bpp or 1024x1024 @ 16bpp. but how? are they just running the display itself much slower? or is it just marketing handwavy "technically it can do this, but noone does" non-sense?
either way there seem to be pretty much no projects around this chip online, so i'd love to see someone throw something together and see how well it works.
The rated speed for the 63484 (8 MHz) is not usually the pixel clock speed, as I understand it. In many ways, the 63484 works like a much more advanced version of the venerable 6845 - it is providing the counters and sync and what not and you need to provide additional hardware like shift registers and pixel clock. bitsavers.org has a lengthy application note and a quite lengthy user manual for it, in addition to the normal datasheet and databook entry.
The application note (
http://www.bitsavers.org/components/hitachi/_dataBooks/U90_Hitachi_HD63484_ACRTC_Advanced_CRT_Controller_Application_Note_198604.pdf) describes several potential hardware configurations. Take a look at page 151, Dot Clock, 2CLK, Load Signal Generation Circuit. The 2CLK is the main clock signal to the chip, is derived by dividing the dot clock per a table in the document. The load signal is also derived by dividing the dot clock, and drives VRAM access and load into the shift registers.
To maximize throughput some memory interleaving to pull multiple bytes at a time from VRAM might be needed. Maybe two bytes like the even-odd scheme in the 80-column Commodore PETs. Or perhaps interleave four banks to pull down four bytes at a time - this would allow for one VRAM memory access cycle to load in 8 pixels of 4bpp color graphics, in the same time frame it could have handled a single monochrome character from one bank of VRAM without interleaving.