Let me be more specific: I don't believe AUC2G53 transmission gates provide best propagation.
Totally on-board with AUC as combinatorial logic, but the transmission gates don't benefit from
triple output totem with diodes and feedbacks. Gate drives maybe, not what is passed through.
Not enough Volts for N to pass logic true, too much P-CH capacitance to fake for the lack of it.

This is the Elmo I don't believe. Measure obvious design flaw and conclude it'll never work.
Analog ring oscillator might not be best use case for AUC's totem or transmission gates.
You also know the pass resistance isn't linear, and highest around the middling voltages.
Was a worthwhile experiment, but not one that proved everything concluded from it.

Look back my AUC drawings and the 1G66 transmission gates are tripled up to better handle
the load of XOR gates. RC in parallel with RC is no faster, its about those loads along the way.
Can't make the smallest XOR gate input any smaller than it is. Instead bond a 3x fatter chain.
I already believed and feared Elmo, just not enough to shave my head and light tea candles.

CBT, with about 2 Volts more on N pass gate than the signal passing under it are a better option.
VDD7V works (probably not for all, but all I've tried) I doubt even these are good as it might get.
We need to look at discreet pass transistors, but I'm OK with CBT for now.

Doubled, tripled, or quadrupled driver at the head of the chain are good advice, but was already
doing that. Last drawing you will see 2.5 ohms for 5ohm, my way of not cluttering the drawing
while implying that two 5ohm gates work in parallel. Even less with the VDD7V trick.

Now update me on the CLA plan for handling decimals. Series chain provides no easy answer.
To have reached a point in life where thinking in decimal makes my head hurt...

Removed by author

"As you can see, the Rdson is growing exponentially with the supply voltage"
No. Supply voltage was a constant 5V for that graph. Sais so at the bottom.
You are reading the graph entirely inside out.

Resistance rises with the voltage in the channel, not on the gate.
Resistance I've measured. <3 Ohms passing 3.3V under CBT VDD7V.

Got the idea to try 7V from capacitive charge pumped SN74CB3Q3253.
Doubles a 3.5V supply to 7 internal volts, and N passes with low ohms.
I would use as-is, but the pump has a 20megaswitch/sec power limit.
https://www.ti.com/lit/ds/symlink/sn74cb3q3253.pdf

I asked myself if 74CBT3253 might be the same pass gate without the
pump power limit? My measurements so far suggest this might be true.
I'm sure there are some that 7V will destroy. Pay money, take chances.

My low tech spaghettis makes unworthy to measure at high speed, but
I know exactly what is going on at low speed. Like resistance and stuff.
Don't take no supergenius to whip out an ohmmeter.

Some day, when I make a real PCB, we can speak of Elmo.
Yes, that is a chain of four SN74CBT3253 SSOP's superglued together.
But left no room onboard for XORs, so the spaghettis still got me.

Not the only one that can copy/paste...


Neither LVC or AUC look much like your theoretical figure 2-4.
Not sure what logic family inspired that graph with a mid dip.
Can't be HC we were looking at, resistance too low to be HC.
TMUX, CB3Q? Something boasting more VGates than 4.5V

TMUX offering greater voltage do not offer fast switching.
Seem more concerned with balancing out charge injection.
CB3Q does switch plenty fast, just can't switch very often.
LVC and CBT may offer best pass-between or pass-under.

"intermediate" "tripling them will add too much capacitance".

Triples both capacitance and conductance. RC remains exactly the same.
No unloaded timing difference three strings separate or bonded together.
Bond is not helping, but also not making worse.

Except the fanload of XOR gates now appears only 1/3 the burden it was.
Would be little point doing same for the Zero chain, as it has but one load.

Let the complaints begin...

Looking back upon this, I see the Overflow XOR gate could have been 5V LVC.
Inputs are 6nS earlier than full results, so plenty of time for the slower gate.
Also plenty of time to buffer the Carry output. Prolly should have done that.

The Zero chain can't progress any faster than Carrys or Borrows are resolved.
But if resistors, buffers, or CLA even out that timing, splitting Zero might help.

No doubt a BLA Borrow tree could be tricked to omit XORvert B at the front end.
But I wonder if a ZLA tree is possible. Can we predict Zero just from raw inputs?
ZLA for math maybe, but to work also for logic functions seems impossible.

Any progress on Decimal? Cause I'm creatively empty and pleading the 2A03,
interrupt, microcode, something, any cheat but actual decimal hardware to
further complicate and slow the works...

Only three and a half MUX repeat per slice. Others and XOR occur once only.
Half an S4S5 MUX is availaibe to another slice. Why I count three n' a half.

Might could merge CARRY8 with BORROW8 using the /OE pins instead.
Let me think on that awhile. Rotates and shifts might still want MUX...

Does it matter specifically what nonsense V produces during rotations?
If any nonsense will do, I am surely producing it. 2G53 controlled by S5
could force the overflow output low, but is there any need?

The bit7 shifter producing an oVerflow XOR input might be redundant to
one producing ARITHMETIC7. Doesn't save any IC to Muntz away a half
MUX, but one less load for the chains. More authentic roto-nonsense-V
than to produce nothing or duplicate CarryOut. Doubt it matters...

I've been thinking (poorly ) about this. The snag is that for arithmetic operations, there are many paths to zero and I think most of them require the ALU to produce them anyway...

• Addition: both inputs zero, or one input the 2s-complement of the other; result zero
• Subtraction: both inputs equal to each other; result zero
• AND: either input zero; result zero
• OR: both inputs zero; result zero
• XOR: both inputs equal; result zero

An eight-bit OR or NOR at each input might provide an early indicator?

Multiplication gets silly, because of all the ways the result might be a multiple of 256; division is easy if the dividend is zero but also needs to consider errors if the divisor is zero.

Neil

Lookahead tree for logic Zero is Karnaugh then NOR8.
Can't make any simpler than straightforward solving.
Greatest problem, no part offers wide enough NOR.
Open drain 74AUC2G06 loaded with current mirror?

No clue if this NotZero could actually work.
Throwing stuff at ceiling to see what sticks.

Obviously NOR style Zero using inverters would be preferable.
Trouble is finding a good enough PNP.

I've tried KSP10 before. Impressive NPN.
Replacement for gold doped MSP10 I think.
Tried as 10MHz DTL, never as Widlar mirror.
650MHz is FT unity gain bandwidth, not
saying the mirror will work as imagined.

Maybe doesn't need mirror, just a -12V rail?
Ground KSP10 base. Pull emitter toward -12V
using emitter resistor that sets the current.
Steal -12V from a MAX232 or something...

-edit- Simpler is better, 600MHz PNP found.
Might throw RF suppressor bead on the base.

Forgot AUC2g06 dual OD inverter. +AUC06 hex leaves no unused spare.

Not so worried for nonsense flag cases, except V for BIT should echo F6.
After studying 6502 instruction set, every flag has cases to deny change.
Thought about multiplexing original values back, but simpler to not clock
unwanted changes into D flipflops. 74AUC1G74 can probably handle that.

6502 has no reverse subtract, so LT GT prolly dumb down to constants.
Only the active low version of Borrow is ever used. Never B-A's Worrob.
Flag override MUX at the head of the chains is overkill for 6502 purpose.
Still need a simple way to disable or ignore chains for purpose of logic.

Getting there slowly...