Fast Discrete FET-Switch ALU

[gfoot]

Squonk wrote:

Then a pure 4-bit FET-switch carry chain is that it is similar to a distributed 4th order RC network with no loop like this:

What FET circuit would this correspond to - is it four FET inverters chained one after another? I guess it would be CMOS-style as otherwise the pull-up resistors would be more limiting than Rdson?

[Squonk]

Removed by author

[Ken KD5ZXG]

El more or less:
Pull down to GND is a much less resistive RC.
Pull up is slower, but only delay to logic true counts.
Initial rise to 0.9V is quite fast. Time to full scale doesn't matter.

We might imagine AUC and CBT have similar balance of R vs C.
But the fanout of XOR gates, open replacement branches, and
other necessary sphagetti are drops in a much larger bucket for
CBT than AUC.

[Squonk]

Removed by author

[Drass]

What a terrific thread this is turning out to be Squonk! It's wonderful to see this survey take shape, and to follow the journey as it evolves. I'll continue to read with interest.

Regarding Elmore delays, they do seem to be a useful model here. It's worth noting that the actual delays I observed in my experiments were much longer than the estimates I derived from Elmore delay calculations (viewtopic.php?p=69813#p69633). Nevertheless I suspect that the central insight (namely that RC delays along the FET-Switch carry chain multiply rather than add together) very much applies in this case.

Quote:

The asymmetry you mention, less resistance to GND than VDD. ... Either might propagate faster from a pre-charged high state.

I like the creative thinking here! The C74-6502 "pre-charged" certain values to accelerate the ALU's Decimal Adjust logic. I don't yet see how this might be used in the FET carry chain, but it sure would be exciting to find out.

While I'm here, I did want to highlight one ALU design consideration that may not be immediately apparent. And that is the important issue of when control signals are required to be available. This is a critical issue for pipelined ALU designs (like the one used in the C74-100, for example), but may also impinge on non-pipelined CPUs with critical timing requirements.

In particular, some ALU designs require that certain control signals be available to the ALU at the same time as (or prior to) the input data. (This is often the case for ALUs that treat control signals as input values to MUX "lookup tables", for example). The consequence is that whatever logic is required to resolve these control signals is pushed upstream in the datapath, either earlier in the cycle (or perhaps to a prior cycle in a pipelined design).

Of course decoding and marshalling of control signals takes time, and unfortunately this processing often ends up on the critical path. In those situations, whatever speed gains the ALU itself delivers should be considered in light of any pre-processing that is required.

By contrast, other ALU designs merely require control signals to select one of several values computed by the ALU. This allows control signals to be resolved even as the ALU itself is working. This has the significant advantage of allowing the ALU to begin work immediately, as soon as data is available, rather than being held up by burdensome control signals.

In the case of the pipelined ALU in the C74-100, this proved a decisive consideration. In that design, data is available to the ALU after just a single Clk-to-Data tpd. Control signals are resolved in parallel with the ALU, and are made available just in time to select an appropriate result to be latched at the end of the cycle.

Alright, I hope the preceding is helpful.

Congrats once again on a great thread.

Best,
Drass

[Squonk]

Removed by author

[Squonk]

Removed by author

[barnacle]

This looks interesting - but to be honest, it's worth it just for the signal names... converse nonimplification? I need one of those

Neil

[Squonk]

Removed by author

[Squonk]

Removed by author

[Ken KD5ZXG]

Regarding CBT3253, there are variants with separate /OE behavior.
The spec sheet internal drawing from a few posts back shows AND.
Both styles of /OE are correct, just be aware when you order.
Or design so unified or separate behaviors won't matter.

/OE confusion goes all the way back to 74153...
I think TI and Phillips were initially different,
then each made a variant to clone the other.

Should also give attention to select pin logic thresholds.
Some 0.9V for 1.8V logic compatibility regardless VDD.
I did not confirm threshold behavior when VDD=7V.
Was happy enough no smoke escaped...

[Ken KD5ZXG]

Squonk wrote:

Hi Neil,

barnacle wrote:

This looks interesting - but to be honest, it's worth it just for the signal names... converse nonimplification? I need one of those

Neil

In logic, a converse nonimplification is a logical connective.

But yes, not all the logical combinations are equally useful

Illogical Gibberish only nonimplifies Gibberish. Anyone with sense should refuse.

Oddballs are less confusing as magnitude comparisons: A>B, A=>B, A<B, A<=B
Converse gibberish, ORNB, ANDNA don't suggest utility, while magnitude does.
But don't want to conflate bitwise logic names with magnitude chain controls.
Why I left mine ORNA whatever, till I figure something better...

There are control line savings by combining the middle Karnaugh columns.
Oddballs and identities lost, but easily restored or faked by other means.
A smaller table of controls without obvious order, hard to memorize...

A carry chain jammed high can also invert logic. Allows S0 to be grounded.

[Ken KD5ZXG]

I switch between carry, borrow, and magnitude a lot. Same as inverse B, don't let it throw you.
Can distort Karnaugh map in twin MUX4 though. That feature abused above to restore oddballs.

[Ken KD5ZXG]

Interesting trio of pass transistors, not easily discovered due to irrelevant description "Dual Voltage Clamp".
How exactly three channels sharing one gate make "dual"? I would wire in parallel as one large pass gate...
https://www.ti.com/lit/ds/symlink/sn74tvc3306.pdf

[Squonk]

Removed by author