Maybe a single bus is a good foundation for your design, but I wasn't thinking of that constraint. (In a TTL design of course it costs more to add busses than in FPGA.) Looking at the 65ce02 datasheet (pdf) we see

and we also see some additional busses in the block diagram (see below)

The same datasheet shows the reduced cycle counts, including many single-cycle instructions (and no page-crossing penalties). Garth has previously mentioned patents covering the elimination of dead cycles, but I haven't yet discovered the patent numbers.

Edit: attached version of image in case imageshack drops the ball.

Off-topic: I got home and I still have the same problem on my laptop running a 32 bit version of windows... I go onto my main computer which has a 64 bit version, and it loads ok. (I did a parite virus check on my laptop, nothing found. That virus has attached itself to .exe files and screwed up other files in the past on my laptop).

On-topic: I have the day off tomorrow, I plan on ordering a few more parts and checking your schematics out. Do you have your version built yet? or partially built?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

No. But I'm busy scraping the parts together. But I first optimize the schematics for the board. For example, the way the 573's are connected to the EEPROM's is not optimal for routing. By swapping 5 lines routing becomes very simple suddenly. I'm not only optimizing it for the auto-router but also for myself: I have to solder the boards by hand.

During this proces I found a bus on 6502-m2 which is an inheritance from the past. Due to other changes it became obselete so I removed it and connected the inputs of the 191's directly to the internal data bus.

I'll keep you informed.

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I heard of the 65CE02 mentioned here on the forums, but I didn't realize how powerful it was compared to the original before I read through the manual last night. Why didn't WDC use this design as it's foundation? or did WDC's version come before this iteration? Is the 65CE02 still being sold?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

As I understand it, the 65CE02 came later than the 65816, and arguably borrowed some ideas from it. The 'CE02 is by Commodore, not by WDC, and I think it didn't happen in any quantity because of marketing or management misses.

In that case it was the CPU meant for the C65, the successor of the C64. Except a number of prototypes, this machine hasn't been produced.

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I remember that a few 3rd-party vendors adopted the 65CE02 for their processor of choice, and I seem to recall that Apple had once experimented with it. Since Woz's DOS relied on CPU instruction timings so heavily, they rejected it in favor of the 65816 for the Apple IIgs.

I do know, however, that the 65CE02 existed for a few years before the first C65 prototype was made. The C65 used a CSG4510A if memory serves me correctly, which has a 65CE02 core, but a handful of other peripherals integrated right on the chip (e.g., both CIA chips, etc.).

I put in a RFQ 3 days ago, for min order. No response yet, although they seem to be well stocked on this IC.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

New update from Dennis, looks like almost final?, on the 6502 on Spartan 3 as of Mar 16, 2010. Such a nice looking board. And to think it has a 6502 at the core. He notes just a few problems with the VHDL code. Beautiful... 'cept for the fact it only runs @ 4MHz.

http://mycpu.selfhost.it/mycpucompact.htm

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Now he's got it up to 34MHz!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Wow. Why so slow? I would have thought an FPGA implementation could go at least in the 60MHz region with today's technology. :/ My lack of FPGA-related experience is showing through here.

(Though, I'm strongly considering a very cheap Windows-based laptop just to tinker around with this stuff.)

A 34MHz 6502 is slow? This is a man's effort to implement another version of 6502 on FPGA with VHDL.. You have something to teach here kc5tja?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Dude, settle down and back off. I only asked a question. What part of, "My lack of FPGA-related experience is showing through here." was not understood?

I think it's cool that he did push it to 34MHz. Other FPGA hackers have reported (non-6502) CPUs up into the 133MHz realm. So, I thought a 6502 implementation could also go at least as fast.

So when does it go on sale?

I'd be delighted if I could run my POC unit at 34 MHz. It barely stays on its feet at 12.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!