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PostPosted: Tue Sep 05, 2023 3:36 am 
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Location: Albuquerque NM USA
Here is a new SBC project. It is a standalone 6502 computer with its own VGA and PS2 keyboard. The 6502 is overclocked to 25.175MHz with 128K system RAM, and 4K dual port video RAM supporting monochrome text display with 64 columns and 48 rows. It has 44-pin IDE for CF disk and a simple bit-bang serial port. It is designed to run DOS/65, the CP/M clone for 6502. It also has 3 RC6502 expansion slots.

Photo of board under construction and schematic.

Already found a problem, the VGA connector should be HD15, not DB15! Another library mistake!
Bill


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PostPosted: Tue Sep 05, 2023 11:45 pm 
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Should prove to be a comprehensive solution - a combination of the CRC65, VGA6448 with it's own expansion bus. Looking forward to more as the bugs get ironed out.


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PostPosted: Wed Sep 06, 2023 12:42 am 
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Larry,
You are exactly right that 65ALL is CRC65+VGA6448+expansion slots. I'm integrating two proven designs, but the unknown is whether it can reliably run 25.175MHz even with expansion slot populated. I thought about a separate clock for 6502, but decided to go with small, integrated solution.
Bill


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PostPosted: Sat Sep 09, 2023 3:27 am 
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Thinking about how to bring up 65ALL. Since I have just concluded the testing of a overclock design with similar hardware consisted of RAM, CPLD, 6502, and CF, it seems logical to port that design to 65ALL to check out the pc board minus the video and PS2 interfaces. So that's what I did; minus the VGA and PS2 interface, the design is mostly the same except CPLD pin assignments are different. It is a matter of reassigning pins and recompiling and program the CPLD. Now I have a bootable 65ALL. It can load the monitor and run memory diagnostically successfully. However, the compact flash interface is not working--it hangs when I try to display CF disk contents. Well, at least I have a working monitor that can load and run diagnostic so this is good progress with minimum amount of works.
Bill


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PostPosted: Sat Sep 09, 2023 7:48 am 
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Great!


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PostPosted: Mon Sep 11, 2023 3:40 am 
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Location: Albuquerque NM USA
An update: I figured out why CF is not working—its setup and access times are based on 14.7Mhz clock. It needs more delay with 25Mhz clock. So now with more delay added, I can bootstrap from the CF disk.

The RAM design is not optimal for 25Mhz access; I should have permanently enabled RAM’s chip select and use 6502’s clock to qualify RAM’s write enable. However, the current design seems to work with 25nS RAM at room temperature and 5V, so I’ll proceed with current sub-optimal RAM design.

The challenge now is fitting the VGA logic and PS2 logic in remaining CPLD resources.
Bill


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PostPosted: Thu Sep 21, 2023 3:07 am 
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The first 65ALL is working fine at 25.175MHz without VGA and PS2 functions. I built up second board to make sure it can also overclocked to 25.175MHz. I cut and jumper RAM's chip select and write enable such that chip select is always enabled to give it longer access time. I also build an adaptor board to correct the VGA connection mistake. This second board will be the reference hardware for adding VGA and PS2 capabilities. I do have the VGA and PS2 functions added to the CPLD, but the big problem is 170 macrocells are needed while EPM7128 only has 128 macrocell! Now I need to do serious design trade-off and optimization. During software development I need a good serial port to load program at 115200, so I'll keep the serial port for now but either have a primitive PS2 function or getting data from serial port instead of PS2. Then later I can have better PS2 function but a primitive bit-bang serial port.
Bill


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PostPosted: Sun Sep 24, 2023 4:14 am 
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I needed more cuts and jumpers to free up CPLD resources, but I managed to retain the serial port and CF functions but squeeze in the text VGA function (still no PS2 function). Now I can bootstrap using serial port and then load & run application programs. This is Game of Life running on the VGA monitor.
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Next step is bootstrapping from CF disk. I only has 32-bytes of ROM space to fit the CF bootstrap routine. This is where the discussion about "smallest CF card bootstrap ROM" becomes very useful. This is definitely a challenging problem.

Once it can bootstrap from CF disk, then porting DOS/65 to it should be possible.

The big problem further ahead is how to have PS2 function to achieve the goal of a standalone 6502 SBC, yet retain some form of serial port function. The serial port is primarily for file transfer between my PC and 65ALL while developing programs on my PC. It could be bit-bang serial at 38400 or even 9600 (yuck!). I can always plug in a serial port expansion board such as the quad-serial based on OX16C954, but that's throwing in the towel and giving up the goal of a single-board standalone 6502. Well, one step at a time...
Bill


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PostPosted: Tue Sep 26, 2023 12:51 am 
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I've received new batch of boards and will be working on other projects, so I'll summarized what has been accomplished on 65ALL for now.

CF bootstrap is working. The code is 32 bytes, 29 bytes plus 6 bytes for NMI, reset, interrupt vectors. I know 29+6 is not 32, but I've overlapped the NMI and low byte of reset vector with JUMP $C020 instruction (opcode $4C20C0) because I've ran out of code space. The interrupt vector is $0200; the reset vector is $FFC0 and the NMI vector is $204C. Ideally I should tune the JUMP instruction to JUMP $C002 (opcode 4C02C0) which will place NMI vector at $024C, but the resource utilization is so tight, it won't compile. This is the CF bootstrap code in CPLD:

Code:
000000r 1               ;9/22/23
000000r 1               ;ROM in CPLD
000000r 1               ;boot from CF disk
000000r 1               ; CF is in native 16 bit mode
000000r 1               ; only the low byte contains meaningful program
000000r 1               ; read data from master boot sector
000000r 1               ;   execute the program in master boot sector to load more program
000000r 1               
000000r 1               ;copy (256-32) bytes file to 0xC020
000000r 1               SerData = $f0f9      ;CPLD serial register
000000r 1               SerStat = $f0f8      ;CPLD serial status, bit 0 is receive ready, bit 1 is txempty
000000r 1               CFdata   = $ee00       ;CF data register
000000r 1               CFerr   = $ee01       ;CF error reg
000000r 1               CFsectcnt   = $ee02       ;CF sector count reg
000000r 1               CF07   = $ee03      ;CF LA0-7
000000r 1               CF815   = $ee04          ;CF LA8-15
000000r 1               CF1623   = $ee05          ;CF LA16-23
000000r 1               CF2427   = $ee06          ;CF LA24-27
000000r 1               CFstat   = $ee07          ;CF status/command reg
000000r 1               
000000r 1                  .ORG $ffc0
00FFC0  1               readbsy:
00FFC0  1  AD 07 EE        LDA CFstat   ;check for Busy (bit7) flag cleared
00FFC3  1  30 FB           BMI readbsy
00FFC5  1  A2 20           LDX #$20   ;issue read CF command and initialize X to $20
00FFC7  1  8E 07 EE        STX CFstat
00FFCA  1               chkdrq:
00FFCA  1  AD 07 EE        LDA CFstat   ;check data request bit set before read CF data
00FFCD  1  29 08           AND #8      ;bit 3 is DRQ, wait for it to set
00FFCF  1  F0 F9           BEQ chkdrq
00FFD1  1               getCFdata:
00FFD1  1  AD 00 EE        LDA CFdata
00FFD4  1  9D 00 C0        STA $c000,x   ;get (256-32) bytes of data to $c020
00FFD7  1  E8              INX
00FFD8  1  D0 F7           BNE getCFdata
00FFDA  1  4C 20 C0        JMP $c020
00FFDD  1               
00FFDD  1               
00FFDD  1               
00FFDD  1  FF              .byte $ff
00FFDE  1  00 02           .word $200


The CF bootstrap waits for CF disk to be ready, write "READ command", and reads the contents of Master Boot Record to memory from $C020 to $C0FF and then jumps into $C020. I'm short on code space but need to initialize regX for the "STA $c000,x" instruction so I used "LDX #$20" and STX CFstat to initialize regX to $20.

The program in Master Boot Record copies 8 sectors (4K) from CF disk to $B000-$BFFF and jumps into $B400. This is the program resides in Master Boot Record:

Code:
;9/24/23
;CFboot for 65all
;collection of programs
; Bootstrap program reside in CF master boot blaock
; Program that writes bootstrap program into CF master boot block
; Program that writes monitor program into CF track 0 area
; Program that write memory diagnostic into CF track 0 area
; Program that write EhBasic into CF track 0 area
;
;At power on bootstrap ROM in CPLD will copy master boot record into $c020 to $c0ff
;  then jump into $c020.  CF is 16-bit mode during the bootstrap operation

SerData = $f0f9      ;UART transmit/receive register
SerStat = $f0f8      ;UART status register
CFdata   = $ee00       ;CF data register
CFerr   = $ee01       ;CF error reg
CFsectcnt   = $ee02       ;CF sector count reg
CF07   = $ee03      ;CF LA0-7
CF815   = $ee04          ;CF LA8-15
CF1623   = $ee05          ;CF LA16-23
CF2427   = $ee06          ;CF LA24-27
CFstat   = $ee07          ;CF status/command reg

;   .pc02         ;use 65C02 instructions

;relocatable program destine for $c020
start:
   LDX #$FF      ;initialize stack pointer
   TXS
   CLD
   LDA #$e0      ;set up LBA mode
   STA CF2427
   LDA #1         ;set feature to 8-bit interface
   STA CFerr
   LDA #$ef      ;the set feature command
   STA CFstat
readbsy:
   LDA CFstat      ;check busy flag
   AND #$80
   BNE readbsy
;load a 4K program (mon65all) stored in track 0, sector $f8-$ff
; to RAM starting from $b000-$bfff
   STA CF1623      ;track 0
   STA CF815
;zero page locations 0xc0 and 0xc1 are indirect index of address to be loaded
   STA $c0         ;put zero in $c0 (LSB)
   LDA #$b0      ;put $b1 in $c1 (MSB)
   STA $c1         
   LDX #$f8      ;read sectors $f8-$ff, start from sector 0xf8
moresect:   
   LDA #1         ;sector count of 1
   STA CFsectcnt
   TXA         ;X contains the sector to be read
   STA CF07
   LDA #$20      ;read CF command
   STA CFstat   
;bit bang transmitter starts here
   STX $c2      ;save X
   LDA #'.'   ;put out a '.' for every sector loaded
   LDY #9      ;shift 9 bits   
   CLC      ;use carry bit as start bit
   ROL      ;move carry into bit 0
   ROL      ;again, because it will be ROR immediately
bitBang1:
;assert a bit for 8.6uS for 25.175MHz clock
   ROR      ;next bit  (2)
   STA SerData   ;bit bang with D(0) (4)
   LDX #$2a      ;(2)
bitTime1a:   
   DEX      ;burn 23x5 clocks (2)n
   BNE bitTime1a   ;(3)n
   DEY      ;(2)
   BNE bitBang1   ;(3)
   INY
   STY SerData   ;stop bit
   DEY      ;initialize Y back to zero
   LDX $c2      ;restore X
;bit bang transmitter ends here         
   
readdrq:   
   LDA CFstat      ;check data request bit set before read CF data
   AND #8
   BEQ readdrq
blk1st:   
   LDA CFdata
   STA ($c0),y      ;save, starting from 0xB000
   INY
   BNE blk1st
   INC $c1         ;next 256 bytes
blk2nd:
   LDA CFdata
   STA ($c0),y
   INY
   BNE blk2nd      ;save a total of 512 bytes
   
   INX         ;next CF sector
   INC $c1         ;next 256 byte of address
   LDA #$c0      ;top of memory to store is 0xBFFF
   CMP $c1
   BNE moresect   
   JMP $b400      ;start location of CRCMon
saveXa:
   .byte 0


There are helper programs that copy several programs into track 0 of CF disk, but I won't bother listing them unless there are interests. It will be uploaded to 65ALL homepage eventually.

So it boots from CF and runs the monitor. Power consumption is 300mA @5V. "The devil is in the detail", there are lots of loose ends to clean up, most important one is an updated PC board.
Bill


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PostPosted: Tue Sep 26, 2023 9:31 am 
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plasmo wrote:
Code:
00FFD1  1               getCFdata:
00FFD1  1  AD 00 EE        LDA CFdata
00FFD4  1  9D 00 C0        STA $c000,x   ;get (256-32) bytes of data to $c020
00FFD7  1  E8              INX
00FFD8  1  D0 F7           BNE getCFdata
00FFDA  1  4C 20 C0        JMP $c020

Great that this all works, the extra stage in the bootloader seems worthwhile.

The only potential saving I see is that you could consider loading to zero page or to the stack, saving one more byte in each case - and making the NMI vector be the same as the bootloader entry point, which could be good or bad. If you used zero page you could also maybe save another byte replacing JMP with BRA, and then have a lot of freedom where to put the NMI entry point.


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PostPosted: Mon Dec 18, 2023 5:06 am 
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I want to cram a lot of functions into a 128-macrocell CPLD that includes 32-byte ROM, RAM decode, compact flash interface, VGA controller , PS2 controller, and serial port. I need the serial port to download program and develop new software, but previous serial port designs were too complex to fit in the CPLD. The simple bit-bang serial port of Muntz65 resolved the resource bottleneck. The bit-bang serial port only require a flip flop for transmit and address decode for receive so I can find room in CPLD to fit it. It is not a reliable serial port because it may drop data when 6502 is busy with other tasks, but as long as it is used for dedicated file transfer, it should work without errors.

The path is now cleared for a standalone 6502 that bootstraps from CF disk, uses PS2 keyboard as input, 64x48 text VGA as output, and CF disk as the mass storage. It has a serial port for software update and program upload. The design is finally taking shape and I've created a homepage for 65all.
Bill


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PostPosted: Mon Dec 18, 2023 5:08 pm 
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Monitor for 65ALL is up and running. It can receive input from either the PS2 keyboard or TeraTerm terminal emulator and output to both VGA monitor and TeraTerm. It is now a standalone computer but it still needs serial connection to workstation for to update system software as well as download application software.

The VGA controller has no hardware scrolling capability but the 64x48 video texts are directly addressable and video text can be written any time without "snow effect" so scrolling is done in software with 25MHz 6502. In fact, when display a screen full of data, the display bottleneck is actually the bit-bang serial transmit. Gordon in his "Project-28" has mentioned a "CTRL-O" command to toggle on/off the bit-bang transmit. That's a good idea, I'm implement that command for 65ALL as well.

Currently 65ALL is running without interrupt. I still have some spare resource in CPLD to generate 60Hz interrupt from vertical sync. Since the interrupt is in sync with vertical sync, in theory I know exactly which pixel of the VGA screen is being painted. I wonder if I can do something interesting with that?
Bill


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PostPosted: Thu Dec 21, 2023 5:34 pm 
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I've changed 65ALL memory map to consolidate ROM and I/O in $F000-$FFFF. This free up 4K space so video RAM and font tables are now from $E000-$EFFF.

25MHz 6502 is fairly capable so I like to see how fast it can run BadApple. The BadApple data is already stored in CF disk in one continuous 4.7MB block. There are 3100 frames that normally run at 20 frames/sec, so 155 seconds duration for the entire video. Each frame is 128x96 pixels black&white so that's 1.5KB per frame. The text-based display is 64x48, 48 rows of 64 texts per row. In order to display 128x96 pictures, 32 fonts are redefined to represent all possible permutations of 2x2 block of pixels. This way each text represents a 2x2 block of pixels, thus 64x48 texts can represent 128x96 pixels.

The program reads 2 bytes of image data, convert that to 4 texts and send them to video RAM and repeat without pause for the entire video. Other than mapping 2x2 pixels into text, there are no compression, just reads video data from CF, maps it to texts, and writes to video RAM. I'm able to play the video in 23 seconds, so that's 6.7 times speed up or 135 frames/sec.

Here is a few seconds of the fast BadApple.
Bill
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PostPosted: Thu Dec 21, 2023 6:08 pm 
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Impressive!


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PostPosted: Thu Dec 21, 2023 7:55 pm 
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plasmo wrote:
The 6502 is overclocked to 25.175MHz...

I keep meaning to ask you if in your overclocked units, are you deriving Ø2 directly from an oscillator, or are you running the oscillator’s output through a flop?

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