Problem sorted.

I wish I could help more, but I'm not versed in the VHDL (My assumption that this is VHDL code).

My SBC-3 CPLD code is written in Abel. Here are the basics that you will need.

If you do not plan to use more than bank 0, then this will be easier. If you want to address the entire 1M of SRAM, then first you need to code a transparent latch from the low 4 bits of the data bus to provide the A16-A19 address lines. Use the rising edge of PHI2 as the latch gate.

Next, you need to establish the ROM and RAM chip selects based on the memory map you desire. Don't forget to account for any IO devices.

Now, set up the RAM read and write signals. Don't forget to use PHI2 to qualify the writes (to prevent writes to invalid addresses where the addresses are not stable yet).

Finally, you need to connect the 65816 data bus to the RAM's data bus.
I used tristate buffers for this. During RAM reads, the data output from the RAM needs to be presented onto the 65816's data bus. During writes, the 65816 data bus outputs need to be gated to the RAM data bus.

My Abel code has documentation to show these steps. You will have to do the equivelent in VHDL. Sorry I cannot help further.

Hope that helps

Daryl

I need to elaborate a little here. There are actually two tristate buffers defined here. One has the 65816 data bus on th D side, and the RAM data bus on the Q side. This is used for RAM Writes. The other is the opposite, with the RAM data bus on the D side and the 65816 databus on the Q side and is used for RAM reads. This acts just like two 74'244's. Direction control uses a combination of R/W and PHI2 along with the RAM Select logic.

Hope that helps even more.

Daryl

Daryl , Thank you very much for your help..

i have successfully run the T65 core on my system.
That will do for the moment . After i will finish vga core (320x240) and other
things i will post the results .

Thank You

Excellent - well done! Look forward to more info.

Hi Bound
any update on your project? Any pictures? Could you perhaps say what FPGA you're using, and whether it's a dev board or your own board?

Cheers
Ed

Hi

Yes , i have some progress , but still lots of things to do.. for some reason i can't make memory to work stable with t65 ( work fine
but single jsr will reset cpu - stack problem ??)
and with real CPU (see video) , simple need more work and time ...

The fpga board i have use in this project was made by digilent , here is the link :
http://www.digilentinc.com/Products/Det ... 17&Prod=D2
but in the final project i I would like to use xc2s100 ... much cheaper.

well.. my cpu board have 65c816 cpu , sid ( c64 music chip)
just for testing , in the final project i I would like to use swinsid ( for more info look here : http://www.swinkels.tvtom.pl/swinsid/ )
, 128 kb flash rom , G65sc51 serial chip , and atmega 128 with avr dos software ( full fat32 support) sd card slot , ps2 mouse and keyboard .

My cpu board

my Fpga board ( temporary in the project)

and some video :
http://www.sendspace.com/file/sp8ymr (16 mb of nothing )

Vga output is 320x320 with 8 bit color/pixel (16 mhz clock) with 8x16 fonts
I have make mistake when i'v make the pictures of cpu board
sid is on 65c51 place.
english is a not my native language so sorry if i have make some mistakes.

Hi Bound
Thanks for the pictures and the video - I suppose the VGA controller is implemented in the FPGA on your D2 board? It looks nice and stable, but not quite bug-free!

When you say the T65 doesn't quite work with the memory, you have a 40-way header and you are substituting for the 65816 on your board?

It's great stuff anyway!

(I've found several versions of T65: the most recent one has "Ver 302 minor timing fixes" in the header of T65_MCode.vhd, and T65.vhd contains the string 'B=1 always on the 6502')

Cheers
Ed

Hi ,

Looks like the reason of the problem i have is in different voltage level.
Spartan 2 Fpga powered with 3,3v is 5v tolerant (in input way) but 65c816 powered with 5v
needs clear signals with ttl logic standard. That's easy to fix for single signal
like irq or clock coming from fpga ( 74hct08 will fix it) but for data bus witch including information for address (above 64K) its not so easy (and will need more pins on fpga) ....
any suggestions ??
Thanks
Edit :
Maybe the right way is to put some cpld like xc9536 between fpga and cpu , maybe cpld's are not so much sensitive and they will work like
hct logic ???

You can get bidirectional octal level shifters - the circuit diagrams for the oho fpga modules show these

BigEd

Thanks for fast replay ..

sure i can , but where is the point to use fpga's and discrete logic ???
just looking for some elegant way

BigEd

At the moment full system is working fine ( problem i had was irq , mib and clk signals going from fpga , hct logic fix it all ) ...
but for some reason i have to reset system few times before it comes stable.
My reset chip is ds1233 output pull up with 1k + to vcc and cap 1nf to gnd .
I already have ps2 keyboard and mouse interface done , and so much ideas
but that simple problem stops me . So if you have any ideas , please contact me.

Just a guess, but are you giving the fpga time to load its programming?

In other words, is the DS1322 reset pin low long enough at power-up for the fpga to get loaded and initialized before it goes high?

Daryl

8Bit:

in my project i have no prom or flash memory to hold fpga configuration for long time Daryl, just uploading configuration from xilinx software any time i do some changes

they are only interface parts so not part of the complexity and not needing updates or fixes. Of course you might prefer a CPLD for other reasons

the parts are 74CB3T3245

After break I'm back to the business .
http://www.youtube.com/watch?v=npS5il8diAk