Hi,

I made some research on the forum and around and I got some contradictory info.

I'd like to know what's the state of the databus, while holding the reset pin low for a NMOS6502. Two
devices need to access the databus only for a few mS. The address bus is left alone, only the 8 bits of the
databus will be used.

Some answers I found state that the databus goes high-Z during reset low, and some other says not.

Is there any real field test that you guys has done on this ?

br
M

Might be relevant: viewtopic.php?f=4&t=5105
Seems like Alarm Siren was designing a system with a similar use case as you have. Maybe they could share some info whether it worked.
Alternatively, you can try posting in that thread - people who replied to that discussion will get notified so you might get a better chance of a response from them.

I'm not an expert in '02 by any means, but I have a hunch that data bus should float while /RES is asserted (maybe not during first few cycles though). Unfortunately the datasheet doesn't seem to mention the exact behavior.

Alternatively, you could probably just halt Ф0 during low cycle to fully release the data bus. However you can't keep it for too long with NMOS '02 because it will start losing its state - viewtopic.php?t=1033

EDIT: There's also Bus Enable pin, but I'm not sure if it has any effect while /RES is asserted.

_________________
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD

Welcome, M!

On a 6502, the databus can be either reading or writing. Reading is the same thing as high impedance, for these purposes. Indeed, at most a few cycles after reset goes low, the databus will be held in read state. How long it takes to get there depends on which cycle of which instruction is running at the time. Hope this helps! (Simulation here for the experts.)

I don't have an NMOS 6502, so I can't do the test you need, but I bet someone here does and can. Meanwhile, the MOS technical manual might have the answer. It is here: http://archive.6502.org/books/mcs6500_f ... manual.pdf

Unfortunately the Bus Enable pin is only present on modern WDC 65c02s, not NMOS ones.

_________________
"The key is not to let the hardware sense any fear." - Radical Brad

hi guys,

I did see the thread that Andrew was talking about, but I didn't want to hijack nor crosspost here and there.

Unfortunately, I know that only the 65c02 has the magic pin BE, but I need to work on systems that use the old 6502A NMOS.

I can take a look with my logic analyzer, how much time the RW pin stay high after the reset but that might be tight, timing wise.

I will have to make some experiment, but I wanted to know if somebody already been that path, of using the databus while keeping the 02 in reset state.

any input from the field test is welcome

thanks!

See the visual6502 simulation I linked - if the 6502 is presently running an instruction which will write, then it may still do those writes even after reset is brought low.

Anyone testing will need to test several situations to catch the 6502 in the worst case behaviour.

It seems that I have a conflict with my Java, so the page doesn't work properly, i'll take to fix this.

If the 6502 still drive the Dbus after the reset low condition, wait a few cycle might clear the path. I'll monitor the Dbus after the
RES is pulled low, on the logic analyzer. At least, this will confirm what's going on.

I believe the RnW pin is more or less hardwired to the databus direction, so you can just monitor that.