That... looks like the wrong capture, or something is very wrong! No prediction errors though, so that's good!


It's not as bad as most of the noise I put up with. Actually the thing that's odd to me there is that it's actually not very noisy - there's no high frequency noise like there is on your clock signal. It's all very low-frequency fluctuations. Is this a resistor-capacitor reset circuit, or something like a DS1813? If it's an RC circuit maybe its own capacitor is smoothing out the high frequencies.

I'd take a look directly at VCC with the scope, to see whether that is varying in a bad way during the clock cycle. It seems likely that the reset signal is just reacting to changes in VCC. If there's a deep spike down in VCC when the clock switches low, for example, that could suck some of the charge out of the reset circuit's capacitor, and it then takes it a while to charge back up.


I don't think I understand what was on that scope I'm afraid.


The capacitors mostly help with sudden demands for current - if the demand isn't short-lived, the capacitors will drain and VCC will be pulled down anyway. In a digital circuit like this, nothing should be pulling a lot of current for a long period of time - it takes a lot of current momentarily to switch states quickly, but shouldn't be a steady state. Maybe an even slower clock will cause it more, and if you do see significant prolonged drops in VCC, something is drawing a lot of current and maybe getting warm to the touch.

I don't know what you're talking about, it looks fine to me... <.< >.>

(All fixed now. That other one was from BDD's ZP RAM test. )

It is a DS1813.

The top was just an unconnected trace. The bottom is D0.

All this is pointing to there still being some problem with VCC. Tomorrow I had better actually check and see how much current the board is really drawing. I'll have a look at VCC on the scope as well. I want to say I did that and it looked fine, but I'm doubting my self.

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"The key is not to let the hardware sense any fear." - Radical Brad

Just a thought: are you being careful about where you connect your scope probe's ground? It needs to be a good connection, to a ground that's closely associated with the driver (or receiver) of the signal you're probing. Probing at the receiver with the receiver's ground should tell you what the receiver will be seeing. Probing at the driver with the driver's ground should tell you what the driver is sending.

Hi Ed,

I don't know if I would say careful. I find that where the probe ground is attached makes less of a difference than people have told me it will. E.g., I see minimal difference on the scope between using one of those little wire springs and just clipping the alligator lead to a short jumper wire. That being said, I've made every IC's ground available on a header pin, and I generally do try to remember to put the ground clip on that pin so I can see just what that IC sees.

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"The key is not to let the hardware sense any fear." - Radical Brad

Sounds like you're on the case! I'm not terribly well-versed myself, I just remember reading various tips.

I did a little more investigating. The whole board draws about 20 mili-amps with the oscillator in and about 5 mili-amps with the oscillator out. I assume that the oscillator is not solely responsible for the entire 15 mili-amp difference there, but that the other ICs are drawing less current since - without a clock - they don't switch!

What I would really like to figure out is the data bus. Here is a scope view of A0 (on the bottom), triggered off the CPU's clock input: I think that looks pretty good. There are a few little wiggles, but nothing that would concern me. The other address lines look similar.

Here's the same scope view, except I moved the probe to D0: At first I thought maybe it was just because the W24512 has weak drivers as Bill suggested. But it looks like that even if I *remove the RAM IC from the board.*

Since the address lines seem fine, and only the CPU drives the address bus, I think that might mean that if only the CPU were driving the data bus it would look fine too. Since the only other thing on the data bus besides the CPU and RAM is the ROM, I think that means that the ROM is responsible. That's hard to test, since the CPU doesn't do anything without ROM! But maybe I could rig up an EEPROM to go in place of the FLASH ROM and see if anything changes. An alternate possibility is, the data bus does go to the edge connector and the address bus doesn't. So maybe I should hook up some address lines to the edge connector and see if that changes anything. I will try both of those this afternoon.

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"The key is not to let the hardware sense any fear." - Radical Brad

Bear in mind that the address lines are always driven by the processor (unless you're into some funky DMA stuff!) and so will generally always see the same load. Data lines are driven by a number of sources; between the processor, RAM, and EEPROM you're seeing at least three different technologies almost certainly with differing loads and drive capabilities... even with the driven part removed, there will still be data cycles where the whole bus is open and floating.

Neil

Hi Neil,

What's concerning me is that the logic high levels seem to be dipping or spiking by +/- 250 mili-volts or so *during a bus cycle.* E.g., the line is being held high around 5.1v, and when the next master clock tock happens you can see it slide down to 4.8v or even less. You can see that happening more clearly on the scope shot from a few posts back. Also, although I didn't upload a picture of this, sometimes the rise times look really slow, like a capacitor charging.

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"The key is not to let the hardware sense any fear." - Radical Brad

On the photo of the D0 line above, I don't see any high levels dipping. I see two distinct high levels, one at rail and one a bit lower, and would assume that this is two different chips each with their own particular output drivers. I don't see anything to worry about.

Well... maybe I am being too fussy. The board *does* seem to work. Thanks Ed!

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"The key is not to let the hardware sense any fear." - Radical Brad

As Ed says; you only care about the logic levels being correct at the time they are sampled/clocked (and of course that the clocking signals don't end up being too close to the transition levels!)

What they do the rest of the time is always going to be a function of stray capacitance and inductance around the circuit, plus the internal design of the part.

Neil

While taking a short break from Blue August to ponder how to improve the design, I took the opportunity to make a little improvement to my workshop that is long overdue: a mini bench-PSU. It doesn't have anything fancy, like variable current / voltage, but it does have a simple two-transistor current limiting circuit that feeds an LM7805 5V regulator through a rectifier diode, so it will provide a nice clean 5V to my breadboards and SBCs, and, hopefully, will keep things from frying long enough for me to notice that something is wrong when I plug my oscillator cans in upside down! It runs off of a 9V wall wart I happened to have laying around, but also works with anything that outputs to a center-positive barrel plug, such as a laptop charger. I couldn't find my 50V electroyltics, so I had to use 16V ones, so maybe I won't power it regularly from my 18V Compaq LTE charger, but it didn't blow up when I briefly tested it.

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"The key is not to let the hardware sense any fear." - Radical Brad

And now back to Blue August! I've been thinking about how to speed things up, and I've come up with two ideas.

One is: use faster parts (low-hanging fruit, there). I like my HC688, but it is very slow. The (much!) faster alternatives have TTL outputs, so I initially didn't consider them at all. I have now overcome my reluctance. At the cost of one pull-up resistor I can use a 74F521 or, even better, a 74ALS521 or `520, and get one gate delay instead of three. (The 520 even has 20k pullup resistors on its inputs, so if I didn't mind moving my I/O window out of ZP and into the upper 32k, I could ditch the resistor network.)

Two is: parallelize things that can be parallelized, such as I/O decoding. The critical pathway for timing is the clock stretch logic. The clock stretches on ROM access, and on slow I/O (such as my 4MHz Rockwell ACIA). The clock stretch logic needs have identified such a condition by 8ns before phi-2 goes high, so that the clock stretcher `166 can load its new value. The current glue logic has to wait 3 gate delays for the HC688 to figure out if it's an I/O access before the AHC138 can decode the specific device. That's already 4 gate delays, not counting the logic needed to check for ROM access. Here is a schematic fragment of the new version: (Sorry, it seems kind of small; I haven't quite got the hang of screenshots on my new laptop.) Anyway, I'm wondering about the value of that pullup resistor. My default value is 3.3k, but that's for tying high input pins on a 65C02, and I'm afraid here it would make the rise time too slow. I don't want the I/O signal to stay low too long (some of the datasheets and app notes I was looking at are contemplating 100ns rise times!) or it will bleed over into the next clock cycle. If I did the math right, I think I could go as low as 220 ohms, but the trade-off there seems to be an awful lot of current.

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"The key is not to let the hardware sense any fear." - Radical Brad

Here is a faster Blue August: I think this might just squeak by at 16MHz. This is pretty close to having my cake and eating it, but I did have to give up the ability to move the I/O window into high RAM. When you're trying to cut close to the bone, one gate delay can be the difference between a 60ns (16MHz) and a 70ns (14MHz) cycle time!

I can actually build this version on the existing Blue August board, with some extensive rewrapping. I would need to combine the LO_RAM and HI_RAM signals into a single RAM_CS, but that wouldn't be a problem.

But, while I've been working on this, I've also been building something else... call it SPC for Standard Pag Computer. Whenever I get into trouble with one of these projects, it seems like it always happens because I've deviated from some general some design principle in order to build some specific thing. Or, maybe a better way to put it is, focusing on building a specific design (from a schematic or whatever) distracts me from the abstract model of good practice. So, I built a kind of philosophical prototype board. With no specific 6502 system in mind, I took one of the same prototype boards that Blue August and Peanutbutter-1 are made of, and I started by tying the VCC and GND buses together in a grid, and putting on a generic pin-header edge connector. Then I started adding IC sockets; not with any particular design in mind, but just trying to fill in the VCC / GND grid in a consistent way that would maximize the use of space: There are five general 14-pin sockets, plus one 14-pin socket wired up to hold a full- or half-can oscillator. There are five 16-pin sockets, and two 20-pin sockets. I included two 28-pin narrow sockets and one 28-pin wide socket, and a socket for a 6502, of course! I desoldered the DS1813 from the first (failed!) Blue August build - no sense in letting it go to waste - and moved it over. I also put on a resistor bank (47k) and some single resistors (3.3k) that can be used for pull-ups/downs. I still need to add some bulk power supply decoupling and some wire-wrap pin headers.

I quite like how it's looking. It may sound silly, but one reason I like it is that the 28-pin socket will let me use my Aries ZIF socket again (I only have a 28-pin one, not a 32-pin one). It just makes a hobbyist's life better!

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"The key is not to let the hardware sense any fear." - Radical Brad

I was reading through it, and looking at the pictures, thinking, "What the heebee's are you even doing?!" But then I realized, "Oh yeah, wire-wrap." I really like your idea here! You've got a good variety of sockets, the placement looks good, and the idea is great. If you have a really solid power/ground grid, then everything else will work out really well

Starting a new project is always ok! We all know our limits to a particular build. Sometimes I do a LOT of bodge wires, sometimes I'm not happy even with one.

So, planning on 16 MHz or 1 MHz, it's neat to see this new style, and it all makes sense for what you do. Thanks for sharing!

Chad