So I've got what is starting to look like an actual circuit going, and before I get too deep into the weeds with this, I'd like to solicit some feedback to make sure I'm not doing anything crazy with this hardware.

A lot of this based on some feedback I've received here and what I've found out on the internet. Some points of interest that I want to make sure I have right:

1) Haven't tried my RTC yet (DS1511Y+), looks like it has a reset circuit which I presume is similar to the one on the DS1813-10, but the datasheet doesn't really specify if I can actually drive the line low like I am. (It does say it's open drain, and requires a pull up, so I'm hoping I'm correct in interpreting that as I can.)

2) The JTAG port, want to make sure I have the correct method for pull up/down resistors there, seems like you can go either way (up or down) according to the interwebs, but I'm not sure about this.

Other notes:
The clock module is going to change to something more sophisticated for debugging and what not.

I'd like to add some expansion ports/pins for doing additional circuits (video, audio, etc)

Any other thoughts you might have are of course welcome!

Here's the PDF, don't think the PNG came out all that clear.

Okay, here's some feedback....

1- The RTC/Reset: This is an overly complicated reset circuit. Also note that the RTC will only drive RST low if the voltage goes under the specified value in the datasheet. Second, the D1 diode is not needed and is backwards, hence you'll never see an interrupt request from the RTC. Also realize that if you manage to get the RTC to trigger an interrupt and not service it, it will persist from a power off/on cycle and just lock the system up. I suggest you remove the diode and replace it with a jumper. For a Reset circuit, perhaps look at a TL7705, which will provide active low and high outputs which are both open collector.

2- The VIA and display: The same applies for D3, not needed as you're using the N version, which is open collector output, and the diode is backwards. For driving the display... I would likely ditch the 138 decode and '04 inverter and just use a single port line for the enable line on the display. Why make it more complicated?

3- CPU address/data lines: What is the purpose of using pull-down resistors on everything? I can't see why they would be needed.

4- CPLD decode: the 1502 is nice, but you're barely using any of it... maybe look at a 22V10, which will handle everything you're doing. Also, I think at least one of the JTAG lines need to be pulled high.

5- Clock circuit: You've chosen a specific oscillator frequency with a question mark for another. What are your goals on a hardware level that pre-req such a specific frequency in the first place?

6- Serial circuit: The reset can he handled per above with the TL7705 and eliminate the '04 inverter. Using the RS-232 level conversion is standard, but are you planning to use this port as a console? If yes, you might consider eliminating the MAX chip and just use a TTL 5V to USB serial interface from FTDI or others.

7- Power supply: Unless you need all of those voltages (+/- 12V, +3.3V) in addition to +5V, that's a lot of extra circuitry, versus a basic 5V regulated supply that can handle 3-5 amps of current, which is more than enough.

Other... perhaps use a DS-1813 and pushbutton on the NMI line as a a Panic button. Having a NMI routine that can restore your basic I/O configuration and getting things back is a plus for debugging.

Hope this helps....

_________________
Regards, KM
https://github.com/floobydust

not bad, a few things that i've noticed:

your JTAG pinout for the CPLD is a bit different to what i usually use, though i don't know if that would cause issues or not.
you have VCC on pin 7, while mine has that NC, and you have pin 10 NC while mine has GND there:


also, i've noticed that you have IO devices that take up between 8 and 32 addresses, but your decoding logic only uses the upper 5 address lines of the CPU.
i assume that means your IO mirrors itself a few times in memory. but why? you have more than enough spare pins on the CPLD, you could connect all 16 address lines and decode the IO devices exactly so they only take up as many addresses as needed so you have more RAM/ROM available.

while on RAM/ROM you seem to have 32kB of RAM in total, but the ROM is only 8kB in size, so like with the IO devices do you just have multiple copies of it in memory? that seems wasteful, why not use a larger RAM IC to have 56kB of RAM and 8kB or ROM, or use a larger ROM like 16-32kB?

why use a series of 3 D-Flip Flops for your Reset signal instead of a DS1813? you already have one on your board, but only use it for the power circuit, so a second one wouldn't hurt for the System Reset as it would save you atleast 1 logic IC a bunch of wiring on a PCB.

another thing, why divide the clock by 4? wouldn't it be enough to divide it by 2 and just use a slower oscillator? or to just run the system a bit faster (if you plan that i would recommend hooking up RDY to the CPLD so you can add a wait state circuit later when you might need it at +10MHz, though that could get tight with the IO pins on the CPLD)

speaking of CPLD, i see the 8 ~DEV lines coming from it, but only ~DEV0-2 are being used for IO devices, the others seem to go nowhere. and there is no expansion connector or similar onboard where they'd go to so what do they do besides taking up IO pins?

and while on the idea of expansion, i wouldn't just waste PA6 and PA7 by leaving them unconnected. personally i would run on LCD in 4-bit mode so that 4 pins on Port-B would be free and bring those out along side PA6 and PA7 (and some VCC and GND pins) to some connector.
that gives you enough IO pins to implement a software I2C or SPI interface with a few chip select lines, which can be useful when messing around with any kind of I2C or SPI device, like SD Cards, various sensors, displays, Microcontrollers, etc.


oh an lastly, U4B and U5B are both spares but you kept them in the Power section instead of along side the other spares in the bottom left corner. it's a minor inconsistency but i thought it was worth commenting on.


.

anyways those are just my thoughts and things i've noticed on the Schematic.

(Always get those diodes backwards.... >_< )

Looks like I need to double check that. I didn't look at the section about setting alarms and what not yet. I was mostly reading details about how the watchdog timer worked. That being said, my understanding was that when the 6502 comes out of reset the interrupt disable status register is set. Is my understanding incorrect?

I had also considered making some sort of a PIC with a (C)PLD which I'd have boot up with interrupts all disabled. (Still exploring this idea)

The reset circuit has the flip flops the provide at least two clock cycle delays. I plan to later replace the clock circuit with a design that will let me select clock speeds, so I can't guarantee the 200ms that from the RTC will generate a long enough reset for the 6502. (more on this later)



I plan to add more devices in the future, which is what the 138 is for. I may or may not keep everything that's attached currently to the VIA. I might replace it all with a keyboard and something else (I don't know what yet.)

This is mostly a holdover from having the 138 on my bread board for testing ideas.



At some point I'd like to figure out how to do some DMA which will require using the bus enable pin. I also have several memory "holes" that are unused and would like them to have a well defined value. The end goal right now is to have a board that I can do some more experimenting with, so I figured having those tied down might be a good idea.

I can certainly remove them if they aren't needed, I was kinda on the fence with having them there in the first place.



I looked at the 22V10, the problem is they only have 10 output pins, and I needed 11! >_<

You're right of course, I'm barely using the 1502 at all, which made me die a bit inside, but I haven't found a smaller PLD that has at least 11 pins.



25.175Mhz is what I have on hand right now, my ultimate aim is to try and get close to the 14MHz speed the 6502 datasheet says the CPU can run at, hence the note. I'm not there yet though, the ROM won't meet the timing requirements at 14Mhz (and I'm possibly already over clocking it slightly with the 6Mhz that it's running at now)

This will require me to figure out some clock stretching which I'm only just now digging into.



(Getting back to the reset circuit)
I'll take a look, I HAD a DS1813-10 there, but when I saw the fact that the RTC I picked out could do that job I figured it would make more sense to remove the extra part in favor, in what I hoped to be, a more simple design. The extra added benefit here is that the RTC will drive the reset line low when the watchdog timer is configured to do so.

I later (after posting the circuit) realized that I could have just used Q' from the flip flops to drive the reset line for the serial port as well.

Initially and right now it is the console yes. Later I plan to try my hand at maybe doing a VGA text display. (Hence why I have the 25.175Mhz oscillator)

The reasoning for the MAX was that if/when I get that done and free up the serial port, I can use it for some other device communication. (Mouse, Modem, other? IDK)

Good chance I could also throw a MAX3421E or VNC2-32L1C for that though.



So the plan here is to pull power from a low* wattage ATX power supply, which provides those extra voltages. If at some point I decide I want to work with something that needs 3.3V (FPGA) or 12V (Floppy drive perhaps?) I'll have it from that, plus a reasonably (I hope) clean supply for 5V. The circuitry I have there is intended to mimic the soft power switch modern PCs have.

* Not that any modern ATX power supply is exactly "low" wattage these days.

I could grab a smaller 5V brick of some sort and use a power regulator to give me 3.3V when I need it. But the ATX supply already did this for me and has standby current for doing other niceties like keeping the the Lith-Ion bat in the RTC charged up.



I'll look into that, I hadn't really decided what to do with the NMI pin yet (if anything).



Thank you! It is most insightful.

Thank you for noting that, I'll double check it.



Upper 6 bits actually.



On my bread board currently are some demultiplexers (a 139 and 138 to be specific).

The memory map worked out to be something like this:
0x0000-0x7FFF = RAM
0x8000-0x9FFF = 8KB Device map
- 0x8000 - 0x83FF = Device 0
- 0x8400 - 0x87FF = Device 1
- 0x8800 - 0x8BFF = Device 2
...
0xA000-0xBFFF = 8KB hole #1
0xC000-0xDFFF = 8KB hole #2
0xE000-0xFFFF = 8KB ROM

This seemed to work nicely with the demultiplexers as well as the RAM and ROM modules I had on hand. I'm kinda happy with this layout. It give plenty of space for each I/O mapped device, and two 8KB holes that I can fill in for video or sound DMA later.

You're correct, I could get really nuanced with the 1502's decoding and make it so that every device doesn't repeat, and honestly I hadn't thought to try, I could squeeze every last drop out of the memory space, but I don't know if the payoff would be worth it in the end.

I'm also still not entirely clear what I am and am not allowed to do with some of the CPLD's pins. In my address decoding (which is dirt simple right now) it seems to be fine assigning pins however I want, but when I started trying to do more complex designs in Verilog, the fitter started complaining about what I was doing (a LOT), so I'm still trying to wrap my head around all of it.



The plan is to eventually replace the clock with one I can switch speeds with. Eventually having one I can single step for debugging. If the system resets in the single step mode, I can't guarantee that the 200ms is long enough for two clock cycles (per the datasheet) to be sent to the 6502.



Good question! That's because all I had on hand at the time was a 25.175 MHz clock. Dividing by two was still too fast for my ROM, and I don't have a clock stretching designed/built yet. Dividing by four gave me a clock speed I could test with on my bread board. I would like to move to a 28Mhz clock to drive the CPU at the 14Mhz it says it can do, and use some clock stretching for the ROM and other slow devices.



The goal is to build a PCB that I can plug breadboards and other things in, probably with some sort of slot like a Eurocard connector, or with a ribbon cable. The extra device lines will go there, I just haven't figured out what I want to do for the ports yet.



The LCD will likely not be sticking around in the long run, especially now that I have a working serial port. It's a hold over from the Ben Eater videos I was watching, it was the quickest way to get some sort of meaningful display other than some blinkin' lights.

Still trying to figure out what I'll do with other I/O. I'm not sure I'm keen on bit banging the SPI from software. I might try using a CPLD to act as some sort of SPI host controller so the 6502 can just communicate with the devices on a byte level.



Yes, those are running on the +V5SB rail, and I wanted to keep them electrically isolated from the parts that were on the regular +5V rail. I'll move them to make things a bit clearer.

Eh I wouldn't recommend clock stretching on a 65C02 as it requires extra circuitry and you already have a CPLD that you could use to drive the RDY pin with (through resistor of course as RDY is bidirectional)
1 or 2 wait states for ROM and IO should be enough up to 16MHz.
Speaking of which, while the CPU is rated for 14MHz it's almost guaranteed that it will run at 16MHz as well, and I'd say a 32MHz oscillator is easier to buy than a 28MHz one.
Or you stay with the 25.175MHz one and run it at 12.6MHz.

Also what's wrong with bigbanging SPI? You just need a single function which could sit in ROM and then you'd have the same byte level communication as you would have with a hardware controller, just slightly slower and without additional hardware.

My USB+RTC module uses SPI, and my SBC has SPI done entirely in software and works perfectly fine, and it's even slower because the send/receive function is written in C.

Plus you don't have to dedicate any of the VIAs IO to it, just bring all unused pins out to a header (with CA/CB, some GND and VCC) and you can decide what to use them for, PS/2 keyboard/mouse, SPI, some parallel device, etc.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Wow,

Lots to unpack. Thanks for the feedback guys!



I know I've at least seen parts of it, though knowing my scatterbrained nature I likely missed/skipped parts that were pertinent.

Okay, think if I continue to stare at this any longer I might go cross eyed. XD

Anyhow, revised (a lot)

Still think I need more around the DMA/RDY pin. (Or am I just over thinking it again?)

Things done:

• Split things up into different pages
• Diodes replaced/fixed
• Removed the 1502 in favor of a pair of ATF16V8Cs (figured out how to do this without chaining them together)*
• Removed the LCD and '138 on the 65C22 and replaced with a generic IDC.
• Replaced the 65C02 PLCC package.
• 65C22N replaced with 65C22S.
• Removed a bunch of the pull down resistors.
• Removed ATX power connector & circuitry.
• Added a debounced button on the NMI line.
• Brought back my debugging clock.

* Yes I know, there's still a 1502 in there, I'm considering using it as a PIC controller. I'm still on the fence about this idea though. I may just replace it with some AND gates; just think it could be handy to have some edge level interrupts.

Still not 100% on that JTAG connector, I find so many different conflicting pin outs for it. >_<


Addressing some specifics from BDD's post:



I figured there was a lot more to this, which falls into the category of analog circuitry, of which I know very VERY little. I figured I was going to sit down and find formulas for this or something, but I wasn't sure what to look for.

I did a bit of reading on this and I can see that yes Schottkys are faster due to a thinner P junction? (Do I have that right? *much confusion*)

I'd like to learn more about this so I can make better decisions on this in the future.



I'm using 3.3K as that is what I have on hand at the moment, finding other values of course is not a problem; but like the above, I don't know how one goes about finding good values for this.

(Digital logic I get, analog, not so much)



I've replaced this ultimately with an 74AC74 and a single ATF16V8C. I did double check the rise/fall times of the 16V8C, it should be within the 5ns period. Thanks for pointing this out to me, I'll be sure to keep that in mind going forward.



Removed, though replaced with some 74AC245s* (I'll get into these in a bit)

I have started to implement the BE/RDY pins so I can later try and develop a DMA for this system.



I was using a DS1813, and I replaced it with the DS1511. The reasoning was fairly simple, I added the DS1511 to get a real time clock, when I realized it had a reset circuit built in, I didn't feel it made sense to keep the DS1813 AND the DS1511 around. The extra flops are/where to count out clock cycles; general indication is this is over kill so I've removed these.

I'd still like to tie the DS1511 into the reset circuit somehow, the watchdog timer in the datasheet looks like it could be very handy if my code should ever hang; I'll consider more about this.

I'm also considering if it would be worth while adding some sort of counter (e.g. a second 65C22) off the square wave as a high resolution timer.



Yep, bad thinking on my part, removed.



Not sure if I will or not, I might; going to go ahead and connect it to the interrupt line for now, and If I need to remove it later I can just break the trace (or use a jumper, which I think is what flooby recommended)



I've removed the ATX power connector; I will point out though that I was considering the idea of connecting an old IDE DVD drive to act as a CD-ROM. That will likely wait until I start moving into the 65816 though.



D'OH! I didn't catch that, the original drawing is not correct, I'm using a 16C550C. I forgot to change the numbers in my drawing, fixed.

I also ditched the MAX per flooby's suggestion.



I've re-read this. I hope I didn't miss any of the finer points, time will tell.

I have added some 245s for the bus, which I'm sure someone will probably call me out on. I know the primer suggested NOT adding these because why would you want to add more gate delays; but I'm not sure what else I plan on connecting in the future and I imagine I can only drive the pins off the 6502 so far.



Clock stretching or using RDY pin for a delay, either way; sounds like the ready pin is the easier route, so I'll work on that adding that next.


Attached is the updated PDF. As before this is a living document so I expect I'll be changing it again before long.

Thanks for the feedback guys! It's been very helpful.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Wired as they are, I don't see why it would matter if the two ATF16V8Cs happen to differ in pin-to-pin prop time. Yuri's circuit would be equally valid using discrete logic in place of the PLD(s)... and even in that scenario I don't see any cause for concern about a timing race.

Not that I'm arguing against the 1502. There are pros and cons to both approaches. For example, board area and component cost/availability are legitimate factors that could sway the decision one way or the other.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

just to throw my 2 cents in, i have never had any external pull-ups on my JTAG lines. i've always just relied in the internal pull-ups that the ATF150x CPLDs have and it seems to be working perfectly fine.