Name     singlestep ;
PartNo   00 ;
Date     15/07/2023 ;
Revision 01 ;
Designer Adrien Kohlbecker ;
Company  - ;
Assembly None ;
Location  ;
Device   f1508ispplcc84 ;

/* Enable pull ups on JTAG interface */

PROPERTY ATMEL { TDI_PULLUP = ON };
PROPERTY ATMEL { TMS_PULLUP = ON };

/* Pin and pinnode definitions */

PIN = CLK;         // CPU PHI2 Clock
PIN = SYNC;        // CPU SYNC Output
PIN = RDY;         // CPU RDY Input (Warning: use open-collector output)
PIN = STEPB;       // Step control input (low-going pulse)
PIN = HALT_RUNB;   // Enable single stepping (high), or run the CPU freely (low)
PIN = INST_CYCLEB; // Single step per instruction (high), or per clock cycle (low)
PIN = IOCLK;       // Stretched clock output

PINNODE = RDY_1;         // Internal RDY bit (needed to implement pseudo open-collector output)
PINNODE = STEP_STATE;    // Internal state storage
PINNODE = STEPB_1;       // STEPB input synced with the clock to prevent metastability (only one needed for double flopping because RDY is also registered)
PINNODE = INST_CYCLEB_1; // INST_CYCLEB input synced with the clock to prevent metastability (only one needed for double flopping because RDY is also registered)
PINNODE = HALT_RUNB_1;   // HALT_RUNB input synced with the clock to prevent metastability (1/2)
PINNODE = HALT_RUNB_2;   // HALT_RUNB input synced with the clock to prevent metastability (2/2)

/* Synchronising inputs to the clock (double-flopping) */

HALT_RUNB_1.D = HALT_RUNB;
HALT_RUNB_1.CK = CLK;
HALT_RUNB_2.D = HALT_RUNB_1;
HALT_RUNB_2.CK = CLK;

STEPB_1.D = STEPB;
STEPB_1.CK = CLK;

INST_CYCLEB_1.D = INST_CYCLEB;
INST_CYCLEB_1.CK = CLK;

/* RDY signal generation */

RDY_1.D = STEP_STATE & STEPB_1;
RDY_1.CK = CLK;
RDY_1.AP = ! HALT_RUNB_2;

/* Pseudo open-collector output, easier than adding the proper option on the command line arguments. */

RDY = 'b'0;
RDY.OE = ! RDY_1;

/* Internal state store */

STEP_STATE.AP = !(STEPB_1 # STEP_STATE);
STEP_STATE.AR = !(!RDY # INST_CYCLEB_1);
STEP_STATE.CK = SYNC;
STEP_STATE.D = 'b'0;
 
/* Output clock streched with RDY (stays high as long as RDY is low) */

IOCLK = CLK # !RDY;