Microbot TeachMover 6502 based Robot Arm, Memory Map

GARTHWILSON · Post by **GARTHWILSON** » Tue Sep 13, 2011 9:01 pm

Quote:

It's attached to PB0, 1 ,2 ,3 inputs on the VIA and generating RX & TX clock on the VIA CB2 output.

It's probably on PB7, since the VIA (if we're talking about a 6522) can output a continuous pulse stream on PB7 without the processor babysitting it. Using it this way is mentioned in my Tip of the Day #11 at viewtopic.php?t=342 . The PB7 frequency is is f/(2(n+2)), where f is the phase-2 frequency, and n is the T1 latch value.

You can also use the SR in mode 100 to continuously shift out a byte over and over (good for a 9-level D/A if you follow it with a filter as mentioned in Tip #5) controlled by a free-running T2, and use the shift clock on CB1. The maximum shift clock frequency then is a quarter of the phase-2 rate. However with this method, only the low byte of the T2 latch is used. The high byte is ignored, unlike the T1-PB7 senario.

Quote:

I would like to modify the Prom code to provide 2400, 4800, 9600, 14400, 19200, 38400, 57600 and 115200,, What I don't know is if the VIA can generate a high enough clock signal for RX & TX to produce those rates

To set T1 to free-run mode and toggling PB7, start by writing 11xxxxxx to the ACR. Although the data book says it causes a continuous stream of interrupts, you don't have to enable the interrupts to come out to the IRQ\ pin. The IER determines whether they do or not. Next, write to the T1 counters. You can write to the latches later if you want to, but you have to write to the counters to get it going, and you do this after writing to the ACR. You will have some frustration if you don't do it in this order.

Quote:

Now 9600 was fast in 1982 but it's snail mail by today's standards.

That's only because we want to transfer pictures, videos, bloatware, humongous help files, etc., which I don't think you'll be doing with an NMOS 6502.

leeeeee · Post by **leeeeee** » Tue Sep 13, 2011 11:16 pm

Quote:

They are changing baud by reading 4 dip switches which allows 16 possible baud rate settings

No, only three of the switches are used.

Quote:

I would like to modify the Prom code to provide 2400, 4800, 9600, 14400, 19200, 38400, 57600 and 115200, Or at-least the highest rate the chips are capable of.

Shouldn't be too hard, part of the reset code and a table will need changing.

It's mostly documented in the updated disassembly archive.

Lee.

falcon5252 · Post by **falcon5252** » Wed Sep 14, 2011 1:04 am

Garth.. I wish it was PB7 but I double and tipple checked it.. My first impression was I had mapped it wrong going by what I was reading on the datasheet.. I thought it had to be PB7 or CB1,, But its definitely Pin 19 CB2 of the R6522A.. I don't get it...

Lee .. So there are only 8 bit rates.. Whats the 4th switch doing.. I didn't know you Had updated the dis-assembly.. Just downloaded it and reading through it.."WOW"
I'm starting to think the easiest fix is drop the 2 lowest baud rates and create 2 new ones using the same clock used for 1200, 2400 or 4800 with with the clock divider set to x1 for 19200 & 38400... Correct me If I'm wrong..

Lee .. VIA pin16 = PB6 DRB bit 6 enter led ,, I rechecked the board and can find no connection to P15 the pendant and no trace leaving the pin 16 on the VIA.. Although it is probably configured as a output as it has no pull-up resistor... All inputs on port a and b have pull-up resistors which are now marked with a * on the wiring chart

Would the changes overrun the 4k Eprom boundary..
Will be adding a 29F010 - 1M (128kb x 8) 70ns CMOS Flash first 8k will be mapped to E000 to FFFF and from C000 to DFFF a paged slot for the rest of the flash memory.. And from 9000 to BFFF will be static ram, 628128LLP-70 - 128Kx8 70ns Low-Power CMOS Ram.. Upper 8k fixed and the lower 8k paged... Don't know if I will ever be able to use it but it will be there..

leeeeee · Post by **leeeeee** » Wed Sep 14, 2011 4:27 am

Quote:

But its definitely Pin 19 CB2 of the R6522A.. I don't get it.

A combination of T2 and the shift register are used to generate the BAUD clock.

Quote:

Whats the 4th switch doing.

Nothing, it is ignored.

It should be possible to add another eight rates but there is little to no room left in the 4K that the ROM fills.

It may be possible to free up the space after the demo program, it seems to end at step 203 and not use the following bytes. Or the demo program could be removed entirely.

Quote:

VIA pin16 = PB6 DRB bit 6 enter led ,, I rechecked the board and can find no connection to P15 the pendant and no trace leaving the pin 16 on the VIA.

I had already guessed the ENTER LED connection from the code and it was confirmed in that last .pdf I linked. It is configured as an output by the reset code and must drive the anode of the LED, cathode to 0V, so that setting the PIN to 1 will light it.

Lee.

falcon5252 · Post by **falcon5252** » Wed Sep 14, 2011 5:34 am

Lee ... If needed 111 to 600 bit rates could be removed to make room, I don't see them ever being used, Phone cradle modems are long gone .. even 1200 is almost useless and could go..

Don't really want to remove the demo It makes it easy to test all the robot motors and see if there are any motion problems... If you do make any mods give it a new file name, so the original code is still available for others to see.. Hope to stay in the 4k boundry for this mod then others with a stock robot could use it .. Not everyone feels like they have to stuff every inch of unused address space with memory.. Its not broke but I still have to fix it..

Did you see any evidence of Acel & Decel ramps in the stepper control code or was it just advertising hyp... I didn't see it notated but then I could have easily missed it..

I can't believe you figured all that out from un-noted binary,,

leeeeee · Post by **leeeeee** » Wed Sep 14, 2011 4:15 pm

Quote:

Did you see any evidence of Acel & Decel ramps in the stepper control code or was it just advertising hyp.

Not there as far as I can see. You could program them by splitting moves into many program steps and running each step with a different speed but any speed you set is global so all the motors will be effected.

Lee.

leeeeee · Post by **leeeeee** » Thu Sep 15, 2011 2:23 am

I've updated the archive. This disassembly includes lines that should allow faster baud rates up to 76800. These lines are commented out by being prefixed with ;## and if used would replace the original lines above them. Only nine bytes are changed.

Lee.

falcon5252 · Post by **falcon5252** » Thu Sep 15, 2011 2:14 pm

Lee .. Nice little code change ... What Windows based Editor / Assembler do you recommend.. Being I have nothing here that will run DOS, Best I can do is XP in a compatibility mode.. Also any good PDF I can download like 6502 ASM for dummies... I recognize most of the code that is the same or similar to 6809 & 6802 that I toyed with in My Heathkit Hero Robot 20+ yr's ago.. But I mostly just copied code snippets or patches and tied them together.. I never really wrote any ASM to speak of... For the last 20 years I've been doing MCU's in Basic-52, Bascom, PICBasic, Mikro Basic, Picaxe and doing PLC Ladder code at work Directsoft 5 and Simatic..

Maybe there is some form of Acel & Decel Ramping in the TeachVAL program... Will have to test it out after I get the drivers fixed.. Still waiting for my parts shipment, They held it up for two weeks for one diode that was out of stock, And never even emailed me about it, Futurlec has great prices but you better not be in a hurry for your order...

I was a Machinist, Electronics Tech & Industrial Control tech at various jobs over the last 35 years but that all ended a few yr's ago when I had a bad reaction to Floxin based antibiotics and it permanently damaged my joints and nervous system.. Now I just sit at home and toy with this stuff to keep from going crazy... The only thing that saved me was I took my pension early and I had my house paid off already when it happened..

leeeeee · Post by **leeeeee** » Thu Sep 15, 2011 3:49 pm

I use Michal Kowalski's 6502 simulator for most 6502 assembly/disassembly/debugging.

His page disappeared sometime ago but I've put up copies of the source archive, program archive and documents archive.

Lee.

falcon5252 · Post by **falcon5252** » Thu Sep 15, 2011 5:55 pm

I downloaded it an opened it in Vista and it ran, Do I need to use a compatibility mode with it, or will it work ok without it..

Also will Michal Kowalski's program compile it to a BIN or HEX file for programming a Prom or do I need a separate program for that

Nightmaretony · Post by **Nightmaretony** » Thu Sep 15, 2011 6:49 pm

The Kowalski will go into several formats, several hex and bin. you need an eprom programmer program, though.

///nother Kowalski lover

//since it is now abandonware, I can make a page to host it, can we get a project to udpate it for other things like 816 or 32 or org32?

BigDumbDinosaur · Post by **BigDumbDinosaur** » Thu Sep 15, 2011 7:29 pm

Nightmaretony wrote:

The Kowalski will go into several formats, several hex and bin. you need an eprom programmer program, though.

///nother Kowalski lover

//since it is now abandonware, I can make a page to host it, can we get a project to udpate it for other things like 816 or 32 or org32?

Incidentally, I have developed a macro set that allows most of the 65C816 native mode instructions to be assembled in the Kowalski simulator. BRL when the branch target is forward of the instruction will not work, as there is a forward reference involved.

Code: Select all

;================================================================================
;
;W65C816S INSTRUCTION MACROS
;
;	---------------------------------------------------------
;	These macros implement W65C816S native mode instructions,
;	as well as 65C02 instructions that are not recognized by
;	the Kowalski assembler (e.g., STP & WAI).
;	---------------------------------------------------------
;
	.if !.ref(brl)
;
brl      .macro .op            ;long relative branch...
         .if .op               ;won't work for forward...
.isize   =3                    ;branches because of forward...
.os      =*+.isize             ;address reference
.os      =.op-.os
             .if .os > 32767
                 .error %1 + ": FORWARD BRANCH OUT OF RANGE"
             .endif
             .if .os < -32768
                 .error %1 + ": BACKWARD BRANCH OUT OF RANGE"
             .endif
             .byte $82
             .word .os
         .else
             .error "INSTRUCTION REQUIRES TARGET ADDRESS"
         .endif
         .endm
;
cop      .macro .op            ;co-processor
         .if .op > $ff
             .error "SIGNATURE MUST BE $00 - $FF"
         .endif
         .byte $02,.op
         .endm
;
jsl      .macro .bk,.ad        ;JSL <bank><addr>
         .byte $22
         .word .ad
         .byte .bk
         .endm
;
jsrix    .macro .op            ;JSR (<addr>,X)
         .byte $fc
         .word .op
         .endm
;
mvn      .macro .s,.d          ;move next <sbnk>,<dbnk>
         .if .s > $ff
             .error "SOURCE BANK MUST BE $00 - $FF"
         .endif
         .if .d > $ff
             .error "DESTINATION BANK MUST BE $00 - $FF"
         .endif
         .byte $54,.d,.s
         .endm
;
mvp      .macro .s,.d          ;move prev <sbnk>,<dbnk>
         .if .s > $ff
             .error "SOURCE BANK MUST BE $00 - $FF"
         .endif
         .if .d > $ff
             .error "DESTINATION BANK MUST BE $00 - $FF"
         .endif
         .byte $44,.d,.s
         .endm
;
pea      .macro .op            ;pea <addr>
         .byte $f4
         .word .op
         .endm
;
pei      .macro .op            ;pei (<addr>)
         .if .op > $ff
             .error "INDIRECT ADDRESS MUST BE $00 - $FF"
         .endif
         .byte $d4,.op
         .endm
;
phb      .macro                ;push data bank register
         .byte $8b
         .endm
;
phd      .macro                ;push direct page register
         .byte $0b
         .endm
;
phk      .macro                ;push program bank register
         .byte $4b
         .endm
;
plb      .macro                ;pull data bank register
         .byte $ab
         .endm
;
pld      .macro                ;pull direct page register
         .byte $2b
         .endm
;
rep      .macro .op            ;clear status register bits
         .if .op > $ff
             .error "OPERAND MUST BE $00 - $FF"
         .endif
         .byte $c2,.op
         .endm
;
sep      .macro .op            ;set status register bits
         .if .op > $ff
             .error "OPERAND MUST BE $00 - $FF"
         .endif
         .byte $e2,.op
         .endm
;
stp      .macro                ;halt MPU
         .byte $db
         .endm
;
tcd      .macro                ;transfer .C to direct page register
         .byte $5b
         .endm
;
tcs      .macro                ;transfer .C to stack pointer
         .byte $1b
         .endm
;
tdc      .macro                ;transfer direct page register to .C
         .byte $7b
         .endm
;
tsc      .macro                ;transfer stack pointer to .C
         .byte $3b
         .endm
;
txy      .macro                ;transfer .X to .Y
         .byte $9b
         .endm
;
tyx      .macro                ;transfer .Y to .X
         .byte $bb
         .endm
;
wai      .macro                ;wait for interrupt
         .byte $cb
         .endm
;
xba      .macro                ;swap B & A accumulators
         .byte $eb
         .endm
;
xce      .macro                ;swap carry & emulation bits
         .byte $fb
         .endm
;
;
;	stack-based accumulator instructions...
;
;	---------------------------------------------------------------------
;	Stack-based accumulator instructions take the form ***S or ***SI, the
;	latter for indexed indirect operations.   *** represents  the  parent
;	instruction.  For example, LDAS 1 is equivalent to LDA 1,S &  LDASI 1
;	is the equivalent of LDA (1,S),Y.  The actual macro names  are  lower
;	case.  The macro comment indicates the official WDC assembly language
;	syntax for the instruction being synthesized.
;	---------------------------------------------------------------------
;
adcs     .macro .op            ;ADC <offset>,S
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $63,.op
         .endm
;
adcsi    .macro .op            ;ADC (<offset>,S),Y
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $73,.op
         .endm
;
ands     .macro .op            ;AND <offset>,S
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $23,.op
         .endm
;
andsi    .macro .op            ;AND (<offset>,S),Y
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $33,.op
         .endm
;
cmps     .macro .op            ;CMP <offset>,S
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $c3,.op
         .endm
;
cmpsi    .macro .op            ;CMP (<offset>,S),Y
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $d3,.op
         .endm
;
eors     .macro .op            ;EOR <offset>,S
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $43,.op
         .endm
;
eorsi    .macro .op            ;EOR (<offset>,S),Y
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $53,.op
         .endm
;
ldas     .macro .op            ;LDA <offset>,S
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $a3,.op
         .endm
;
ldasi    .macro .op            ;LDA (<offset>,S),Y
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $b3,.op
         .endm
;
oras     .macro .op            ;ORA <offset>,S
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $03,.op
         .endm
;
orasi    .macro .op            ;ORA (<offset>,S),Y
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $13,.op
         .endm
;
sbcs     .macro .op            ;SBC <offset>,S
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $e3,.op
         .endm
;
sbcsi    .macro .op            ;SBC (<offset>,S),Y
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $f3,.op
         .endm
;
stas     .macro .op            ;STA <offset>,S
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $83,.op
         .endm
;
stasi    .macro .op            ;STA (<offset>,S),Y
         .if .op > $ff
             .error "OFFSET MUST BE $00 - $FF"
         .endif
         .byte $93,.op
         .endm
;
;
;	16 bit immediate mode instructions...
;
;	--------------------------------------------------------------------
;	Immediate mode instructions that are able to accept 16 bit  operands
;	take the form ***W, where *** is the parent 8 bit  instruction.  For
;	example, ADCW is the 16 bit form of ADC.  The actual macro names are
;	lower case.   It is the responsibility of the  programmer to  assure
;	that MPU register sizes have been correctly configured before  using
;	***W instructions.  For example:
;
;		LONGA                 ;16 bit .A & memory
;		LDAW $1234            ;equivalent to LDA #$1234
;		SHORTA                ;8 bit .A & memory
;		LDAW $1234            ;won't work as expected!!!
;
;	The macro comment indicates the official WDC assembly language  syn-
;	tax for the instruction being synthesized.
;	--------------------------------------------------------------------
;
adcw     .macro .op            ;ADC #nnnn
         adc #<.op
         .byte >.op
         .endm
;
andw     .macro .op            ;AND #nnnn
         and #<.op
         .byte >.op
         .endm
;
bitw     .macro .op            ;BIT #nnnn
         bit #<.op
         .byte >.op
         .endm
;         
cmpw     .macro .op            ;CMP #nnnn
         cmp #<.op
         .byte >.op
         .endm
;
cpxw     .macro .op            ;CPX #nnnn
         cpx #<.op
         .byte >.op
         .endm
;
cpyw     .macro .op            ;CPY #nnnn
         cpy #<.op
         .byte >.op
         .endm
;
eorw     .macro .op            ;EOR #nnnn
         eor #<.op
         .byte >.op
         .endm
;
ldaw     .macro .op            ;LDA #nnnn
         lda #<.op
         .byte >.op
         .endm
;
ldxw     .macro .op            ;LDX #nnnn
         ldx #<.op
         .byte >.op
         .endm
;
ldyw     .macro .op            ;LDY #nnnn
         ldy #<.op
         .byte >.op
         .endm
;
oraw     .macro .op            ;ORA #nnnn
         ora #<.op
         .byte >.op
         .endm
;
sbcw     .macro .op            ;SBC #nnnn
         sbc #<.op
         .byte >.op
         .endm
;
;
;	register size macros...
;
;	--------------------------------------------------------------------
;	These macros are a convenient way to change the MPU's register sizes
;	without having to remember the correct bit pattern for the REP & SEP
;	instructions.
;	--------------------------------------------------------------------
;
longa    .macro                ;16 bit accumulator & memory
         rep $20
         .endm
;
longr    .macro                ;16 bit all registers
         rep $30
         .endm
;
longx    .macro                ;16 bit index registers
         rep $10
         .endm
;
shorta   .macro                ;8 bit accumulator & memory
         sep $20
         .endm
;
shortr   .macro                ;8 bit all registers
         sep $30
         .endm
;
shortx   .macro                ;8 bit index registers
         sep $10
         .endm
;
;
;	INT instruction - assembles as BRK followed by operand...
;
int      .macro .op            ;INT <intnum>
         .if .op > $ff
             .error "INTERRUPT NUMBER MUST BE $00 - $FF"
         .endif
         .byte $00,.op
         .endm
;
	.endif
	.end

Incidentally, the simulator *assembles* programs, not *compiles* them.

-----
I updated the macro listing to fix a typo that was recently discovered.

--BDD

falcon5252 · Post by **falcon5252** » Thu Sep 15, 2011 7:54 pm

Tony ... I'm just going by what Lee Recommended.. And I just downloaded it 15 min ago so I have no Idea what it is capable of.. Besides I don't see allot of alternatives that will run in windows.. So are there any windows based Compilers, And which do you recommend... I have a Prom Programmer but it's a piece if junk, But it let me extract the binary from the Robots Prom... Just hoping it will program the Fash Mem I bought to replace the original Prom...

Wheres a good place to buy a 4mhz or faster 65802 & 65C02P4 at a decent price that takes Paypal.. I know its not ebay 65C02P4 listed at $79

Do the 65802's default to 8 bit mode or do they need a command in the Prom reset vector to set the Mode..

Lee... How are they creating the stepper step and speed timing routines, And would it be a major or minor change to get it to run on a faster processor.. With a clock divider circuit for slow I/O including ACIA and VIA all timed events there should run at the same speed.. I think therefor I could be wrong...

leeeeee · Post by **leeeeee** » Thu Sep 15, 2011 7:58 pm

Quote:

since it is now abandonware, I can make a page to host it,

I've found a current email address for Michal and have asked him for permission, I'm just waiting on a reply.

Quote:

can we get a project to udpate it for other things like 816 or 32 or org32?

As it's written in Microsoft Visual C a lot of it is pretty impenetrable. I've asked about this before and the consensus seemed to be it would be easier to write a new program than port this one to C++.

Lee.

Nightmaretony · Post by **Nightmaretony** » Thu Sep 15, 2011 8:02 pm

Ah, ok. Sigh. Was hopping to see a more open source version that is easier to update and maintain...

Microbot TeachMover 6502 based Robot Arm, Memory Map

Kowalski Simulator