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The RTF65002 Core
Posted: Sun Sep 01, 2013 8:55 am
by Rob Finch
Just announcing that I'm working on an 32 bit core that has an 6502 emulation mode.
It's a 16 reg design. Instruction and data caches. 32 bit word oriented addressing.
http://www.finitron.ca/Projects/Prj6500 ... 002ppp.htm
Re: The RTF65002 Core
Posted: Sun Sep 01, 2013 3:32 pm
by barrym95838
I like it!!!!
Can you show us some 'real world' code fragments of familiar routines, like a memory move or a simple sort? If you want to get Garth's attention (like I wanted to do), you could show us how some Forth primitives could be extended to 32-bits. The backwards-compatibility makes it instantly useful, but obviously fails to make the best use of its capabilities, so it would be nice to see how some 6502 code looks after the 'upgrade'.
Sincerely,
Mike
Re: The RTF65002 Core
Posted: Sun Sep 01, 2013 3:56 pm
by Rob Finch
Sure, I can post some code samples. I've been working through a couple.
Unfortunately I don't know Forth. I could try translating a couple routines if I had samples.
The following is a typical print string to serial port routine.
Code: Select all
cpu RTF65002 ; tell assembler which instruction table to use
; If the program gets here then we know at least the boot strap
; worked okay, which is in itself a good test of processor health.
23 000009000 22 38 A6 00 00 jsr putmsg3
24 000009005 54 65 73 74 69 6E 67 20 db "Testing Processor", 13, 10, 0
24 00000900D 50 72 6F 63 65 73 73 6F
24 000009015 72 0D 0A 00
....
1372 00000A638 putmsg3
1373 00000A638 FA plx ; pop the return address off the stack
1374 00000A639 pm5
1375 00000A639 B5 20 01 00 lb r1,$0,x ; load byte into accumulator
1376 00000A63D E8 inx
1377 00000A63E 05 11 00 ora #0 ; test for end of string
1378 00000A641 F0 06 beq pm6
1379 00000A643 62 09 00 bsr putSer
1380 00000A646 80 F2 bra pm5
1381 00000A648 pm6
1382 00000A648 7C 00 00 00 00 jmp ($0,x) ; return to next code byte
; put character to serial port
; test and,bne,pha,pla,sta,lda,rts
1387 00000A64D putSer
1388 00000A64D 48 pha ; temporarily save character
1389 00000A64E ps1
1390 00000A64E 0D 10 01 CF 00 00 lda UART+1 ; get serial port status
1391 00000A654 25 11 08 and #XMIT_FUL ; is it full ?
1392 00000A657 D0 F6 bne ps1 ; If full then wait
1393 00000A659 68 pla ; get back the char to write
1394 00000A65A 8D 01 00 CF 00 00 sta UART ; write it to the xmit register
1395 00000A660 60 rts
Re: The RTF65002 Core
Posted: Sun Sep 01, 2013 6:02 pm
by Rob Finch
Memory move UP/DOWN modified from the source code repository
Code: Select all
; Move memory down
;
; FROM = source start address
; TO = destination start address
; SIZE = number of bytes to move
;
Finitron 65002 assembler version 1.0 Sun Sep 01 13:54:07 2013 Page 31
t65002.asm
1800 = 10 SIZEM EQU $10
1801 = 11 FROM EQU $11
1802 = 12 TO EQU $12
1407 00000A661 02 03 33 MOVEDOWN AND R3,R3,R0 ; load Y with zero
1408 00000A664 B6 00 01 LDX SIZEM
1409 00000A667 F0 0D BEQ MD4
1410 00000A669 11 30 11 01 MD1 LDA (FROM),Y
1411 00000A66D 91 31 20 01 STA (TO),Y
1412 00000A671 C8 INY
1413 00000A672 CA DEX
1414 00000A673 D0 F5 BNE MD1
1415 00000A675 60 MD4 RTS
; Move memory up
;
; FROM = source start address
; TO = destination start address
; SIZE = number of bytes to move
;
1423 00000A676 B4 00 01 MOVEUP LDY SIZEM ; the last byte must be moved first
; start at the final pages of FROM and TO
1425 00000A679 F0 0F BEQ MU2
1426 00000A67B 88 MU1 DEY
1427 00000A67C 11 30 11 01 LDA (FROM),Y
1428 00000A680 91 31 20 01 STA (TO),Y
1429 00000A684 02 03 10 CMP R3,R0 ; compare Y to zero
1430 00000A687 D0 F3 BNE MU1
1431 00000A689 MU2
1432 00000A689 60 RTS
Re: The RTF65002 Core
Posted: Sun Sep 01, 2013 10:38 pm
by ElEctric_EyE
I quickly skimmed the page. Looks good! But a few questions.
So it has 16 32-bit registers?
The 1st 4 are dedicated to 65c02? Acummulator, X and Y registers? With another register always zero, for the STZ instruction?
Then the user has another 12 32-bit registers?
Re: The RTF65002 Core
Posted: Mon Sep 02, 2013 2:30 am
by Rob Finch
So it has 16 32-bit registers?
The 1st 4 are dedicated to 65c02? Acummulator, X and Y registers? With another register always zero, for the STZ instruction?
Then the user has another 12 32-bit registers?
Yes, 16 regs available! In 32 bit mode the STZ instruction is just a store R0 (ST R0,....) so I hijacked the STZ opcode to use as a store byte instruction instead.
(The docs are a little out of date - I've decided to add a couple of byte load and store instructions.). The ST instruction uses the STA opcode set, but can store any of the registers, so it made STZ/STX/STY redundant, excepting for shorter forms.
There is also two stack pointer registers, one for each mode. This is to allow the processor to handle interrrupts by automatically switching to native mode.
A separate stack pointer is needed to avoid problems with the stack pointer needing to be word aligned for 32 bit mode.
I need to store an interrupt policy bit somewhere. The policy being whether or not to switch to native mode for interrupts.
Re: The RTF65002 Core
Posted: Mon Sep 02, 2013 4:08 am
by barrym95838
What assembler are you using, Rob? So far, I've been hand-assembling my 6502 to 65m32 translations, and I'm getting pretty good at it. However, it's obvious that I will need to modify an existing assembler soon, and I don't want to spend any money on one yet. Would you be able to share any helpful info and/or source code for your assembler, assuming that it is available and in a language that I can understand well enough to modify?
If this request is too personal, just say so ... I'll understand.
Mike
Re: The RTF65002 Core
Posted: Mon Sep 02, 2013 6:36 am
by Rob Finch
What assembler are you using, Rob? So far, I've been hand-assembling my 6502 to 65m32 translations, and I'm getting pretty good at it. However, it's obvious that I will need to modify an existing assembler soon, and I don't want to spend any money on one yet. Would you be able to share any helpful info and/or source code for your assembler, assuming that it is available and in a language that I can understand well enough to modify?
I'm using an assembler I wrote myself; it's a 6502 macro assembler that's TASS compatible. I haven't actually finished updates for the RTF65002 yet.
Sorry, but I can't really offer source code. The assembler is quite powerful and written in C++ using object heirarchies, so there is a steep learning curve to the assembler. It is table driven, but not that easily modified. It's thousands of lines of code, something one probably doesn't want to start with.
I would suggest finding a simpler assembler written in C to modify, I think there was a 6800 assembler with source code available on the net. I wrote my first assembler years ago for the 6800 back in school and have been updating it ever since.
Are there docs for the 65m32 ?
Re: The RTF65002 Core
Posted: Mon Sep 02, 2013 7:38 am
by barrym95838
... [snip] ...
I would suggest finding a simpler assembler written in C to modify, I think there was a 6800 assembler with source code available on the net. I wrote my first assembler years ago for the 6800 back in school and have been updating it ever since.
Thanks, Rob. I have several possibilities, but haven't settled on one yet.
Are there docs for the 65m32 ?
Good question. The design has matured in my head for several years, but I spilled the beans a little bit early here, before I had anything on paper that was truly fit for public consumption:
viewtopic.php?f=1&t=1419&start=125
... and I have been struggling to complete the specification document ever since. Apparently, the
65m32's operand structure that is so crystal-clear in my head is not so easy for me to explain clearly in print, except for the code translations that roll out so easily for me. It's a work in progress, but I have been receiving some private help and encouragement from
Garth and
Dieter, among others. With any luck, it should be ready for public view within the next couple of weeks. Finishing the spec doc is my primary concern now, just below sleep, full-time job, and family. After I can call it 'complete', I should be able to modify and extend
teamtempest's 16-bit CPUSim core, which he kindly provided, and decide on an assembler.
Take care,
Mike
Re: The RTF65002 Core
Posted: Tue Sep 03, 2013 5:04 pm
by ElEctric_EyE
Rob, how far along on your core percentage-wise? What kind of hardware are you testing it on?
Re: The RTF65002 Core
Posted: Tue Sep 03, 2013 11:07 pm
by Rob Finch
Rob, how far along on your core percentage-wise? What kind of hardware are you testing it on?
There's still a long ways to go (1%?). I've got enough coded to begin testing. There could still be glaring ommissoins of things I want to see in the core that I'll find by testing. I just added a register indirect jump today, how I missed that I don't know.
I have it testing in simulation fetching instructions correctly through both cached and non-cached access. The branches all seem to be working. It also seems to handle the NMI interrupt okay.
For simulation I'm testing on an HP ENVY workstation. 12 GB ram, Quad core 4?GHz. Windows 8. Using Xilinx's ISE Webpack and ISIM.
For real hardware, I've got an Digilent Atlys board to test with.
The core is currently about 850 regs and 8300 lookup tables. Synthesis reports it should run at about 50MHz.
The core is about eight times the size of an '02 core, and hence also slower.
Re: The RTF65002 Core
Posted: Thu Sep 05, 2013 3:26 am
by Rob Finch
Well I may be 2% done now. I've managed to run the 65C02 emulation through a processor test program.
The core has grown somewhat to about 8700 LUTs with bug fixes and performance optimizations.
I'm wondering about adding a software interrupt mechanism for BIOS/OS support. Many processors have this, but I don't want to get too complex.
Re: The RTF65002 Core
Posted: Sun Sep 08, 2013 10:03 pm
by Rob Finch
Well a built a "little" test system, and
"RTF65002 system starting." displays on the screen, after several bug fixes.
The processor running in 32 bit mode with i-cache enabled.
I forgot to set the flags after register-register operations, which resulted in the message displaying vertically, initially.
The i-cache tags also had to be initialized to invalid.
I also double the size of the i-cache to 16kB in balancing resource usage.
Re: The RTF65002 Core
Posted: Wed Sep 11, 2013 8:17 am
by Rob Finch
I've got a processor test system up and running in hardware on an FPGA board.
I've managed to get an interface to EhBASIC working. I supplied routines for char get and char print, and *almost* have EhBasic working in emulation mode. BASIC gets an overflow error at the memory size prompt, but the fact I get a prompt shows the interfacing is working. Kinda cool because it's calling a routine running 32 bit code from eight bit code.
Code: Select all
DisplayChar = $FFFFC000
KeybdCheckForKeyDirect = $FFFFC004
KeybdGetCharDirect = $FFFFC008
.....
; system dependant i/o vectors
; these are in RAM and are set by the monitor at start-up
V_INPT
JMP (VEC_IN) ; non halting scan input device
V_OUTP
JMP (VEC_OUT) ; send byte to output device
V_LOAD
JMP (VEC_LD) ; load BASIC program
V_SAVE
JMP (VEC_SV) ; save BASIC program
; ===== Output character to the console from register r1
; (Preserves all registers.)
; Does a far indirect subroutine call to native code.
;
V__OUTP:
nat
cpu rtf65002
pha
phx
ldx #0
jsr (DisplayChar>>2,x) ; should not trash char
plx
pla
emm
cpu W65C02
and #$FF ; set Z, N according to char in accumulator
rts
Re: The RTF65002 Core
Posted: Wed Sep 11, 2013 5:32 pm
by barrym95838
Hey Rob,
I think that I read somewhere that Lee used BCD mode in one or two places in EhBasic. I'm not sure if this is pertinent to your error, but it might be worth investigating. Klaus has an exhaustive test suite that checks both modes and all condition flag side-effects ... if your core is fast, it shouldn't take long to run it and see if you nailed all of the flag effects in your emulation mode.
Good luck,
Mike