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visrealm
PostPosted: Tue Jan 25, 2022 4:44 am 
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Hi all,
I've been developing an emulator for my 6502 build (the HBC-56). After playing with some other 6502 libraries, I decided to write my own (yes... another 6502 library).

It's standard C99, no dependencies. Has a sample test program and even passes the following Klauss Dormann tests:

  • 6502_functional_test
  • 6502_decimal_test (with valid BCD only)
  • 65C02_extended_opcodes_test

Includes:

  • Support for standard 6502, 65C02, WDC65C02 and R65C02.
  • All WDC and Rockwell-specific instructions.
  • Correct handling of Decimal mode.
  • Accurate instruction timing.
  • User-supplied I/O callbacks.
  • IRQ and NMI signals.
  • Multiple CPU instances.

Feel free to check it out here: https://github.com/visrealm/vrEmu6502

Also, if you're looking for a TMS9918 emulator or a Character LCD emulator, I've written those too. Same deal, C99, no dependencies.

Constructive criticism welcome.

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barrym95838
PostPosted: Tue Jan 25, 2022 5:12 am 
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visrealm wrote:
Constructive criticism welcome.

He should be around shortly. :roll:

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BigEd
PostPosted: Tue Jan 25, 2022 7:54 am 
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That's great Troy! Always good to see a new emulator, but especially good to see minimal dependencies, passing a test suite, and open source!
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Dr Jefyll
PostPosted: Tue Jan 25, 2022 3:40 pm 
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Quote:
  • 65C02_extended_opcodes_test
The undefined NOPs? Nice to see these included, as there's certain small but very real use for these. (And luckily they're much simpler than the undefined opcodes on an NMOS 65xx! :shock: )

Are you worried at all about the emulated interrupt latency being 100% correct? If so, be aware that each 1-byte, 1-cycle NOP delays interrupt recognition by one cycle. That is, the interrupt won't be recognized until an instruction is encountered which is NOT a 1-byte, 1-cycle NOP.

Just curious -- did you manage to unravel exactly how the 'C02 responds to the undefined opcode $5C? I know it's 3 bytes and 8 cycles. But there's a memory access that probably varies according to the last 2 bytes of the instruction...

-- Jeff

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visrealm
PostPosted: Tue Jan 25, 2022 10:29 pm 
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BigEd wrote:
That's great Troy! Always good to see a new emulator, but especially good to see minimal dependencies, passing a test suite, and open source!


Thanks, Ed.

Dr Jefyll wrote:
Quote:
  • 65C02_extended_opcodes_test
Are you worried at all about the emulated interrupt latency being 100% correct? If so, be aware that each 1-byte, 1-cycle NOP delays interrupt recognition by one cycle. That is, the interrupt won't be recognized until an instruction is encountered which is NOT a 1-byte, 1-cycle NOP.


I wasn't aware of this one. I'm not concerned about it for my uses, but... nice to know. Thanks!

Dr Jefyll wrote:
Quote:
  • 65C02_extended_opcodes_test
Just curious -- did you manage to unravel exactly how the 'C02 responds to the undefined opcode $5C? I know it's 3 bytes and 8 cycles. But there's a memory access that probably varies according to the last 2 bytes of the instruction...


I'm treating it as an ABS address mode instruction. So it will treat the following 2 bytes as an absolute address and read it, but obviously do nothing with it. I haven't verified this against a real 65C02.

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visrealm
PostPosted: Tue Jan 25, 2022 10:59 pm 
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Dr Jefyll wrote:
Are you worried at all about the emulated interrupt latency being 100% correct? If so, be aware that each 1-byte, 1-cycle NOP delays interrupt recognition by one cycle. That is, the interrupt won't be recognized until an instruction is encountered which is NOT a 1-byte, 1-cycle NOP.


So... I wasn't worried about it. But, I read up on it and got a bit of a twitch in my eye...

Now I've implemented that too. 8)

Thanks again.

Edit: I've also set the correct address modes for the various LDD opcodes (except $5C).

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visrealm
PostPosted: Wed Jan 26, 2022 3:25 am 
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Updated my test runner to include a few output options. Mainly for filtering output, and monitoring RAM.

Now getting average MHz and MIPs at the end too. :D

The result will be heavily impacted by the output options. Obviously quiet mode for a better result.

Code:
Usage:
vrEmu6502Test [OPTION...] <testfile.hex>

Options:
  -c <cpumodel>     one of "6502", "65c02", "w65c02", "r65c02". defaults to 65c02.
  -i                output instruction count on each row
  -f <lines>        filter output to every #<lines> lines
  -h                output help and exit
  -m <from>[:<to>]  output given memory address or range
  -q                quiet mode - only print report
  -r <addr>         override run address
  -v [<count>]      verbose output from instruction #<count>


Code:
> vrEmu6502Test -c w65c02 -q -m 0x08:0x0f -v 21986970 programs\65C02_extended_opcodes_test.hex
  -------------------------------------
          vrEmu6502 Test Runner
  -------------------------------------
    Copyright (c) 2022 Troy Schrapel
  https://github.com/visrealm/vrEmu6502
  -------------------------------------

Running test:                "programs\65C02_extended_opcodes_test.hex"

Options:
  Processor model:           Western Design Centre 65C02
  Output filtering:          Quiet until #21986970
  Output memory:             $0008 - $000f
  Start address:             $0400


Instr #     PC     Instruction    Acc    InX    InY    SP        Status      $0008 - $000f

#21986970   $2496: lda #$99      A: $99 X: $0e Y: $ff SP: $ff F: $f8 NVD...  $00 $00 $bd $ad $01 $00 $00 $00
#21986971   $2498: sta $0d       A: $99 X: $0e Y: $ff SP: $ff F: $f8 NVD...  $00 $00 $bd $ad $01 $99 $00 $00
#21986972   $249a: lda $0e       A: $00 X: $0e Y: $ff SP: $ff F: $7a .VD..Z  $00 $00 $bd $ad $01 $99 $00 $00
#21986973   $249c: beq $24d7     A: $00 X: $0e Y: $ff SP: $ff F: $7a .VD..Z  $00 $00 $bd $ad $01 $99 $00 $00
#21986974   $24d7: cpx #$0e      A: $00 X: $0e Y: $ff SP: $ff F: $7b .VD.CZ  $00 $00 $bd $ad $01 $99 $00 $00
#21986975   $24d9: bne $24d9     A: $00 X: $0e Y: $ff SP: $ff F: $7b .VD.CZ  $00 $00 $bd $ad $01 $99 $00 $00
#21986976   $24db: cpy #$ff      A: $00 X: $0e Y: $ff SP: $ff F: $7b .VD.CZ  $00 $00 $bd $ad $01 $99 $00 $00
#21986977   $24dd: bne $24dd     A: $00 X: $0e Y: $ff SP: $ff F: $7b .VD.CZ  $00 $00 $bd $ad $01 $99 $00 $00
#21986978   $24df: tsx           A: $00 X: $ff Y: $ff SP: $ff F: $f9 NVD.C.  $00 $00 $bd $ad $01 $99 $00 $00
#21986979   $24e0: cpx #$ff      A: $00 X: $ff Y: $ff SP: $ff F: $7b .VD.CZ  $00 $00 $bd $ad $01 $99 $00 $00
#21986980   $24e2: bne $24e2     A: $00 X: $ff Y: $ff SP: $ff F: $7b .VD.CZ  $00 $00 $bd $ad $01 $99 $00 $00
#21986981   $24e4: cld           A: $00 X: $ff Y: $ff SP: $ff F: $73 .V..CZ  $00 $00 $bd $ad $01 $99 $00 $00
#21986982   $24e5: lda $0202     A: $15 X: $ff Y: $ff SP: $ff F: $71 .V..C.  $00 $00 $bd $ad $01 $99 $00 $00
#21986983   $24e8: cmp #$15      A: $15 X: $ff Y: $ff SP: $ff F: $73 .V..CZ  $00 $00 $bd $ad $01 $99 $00 $00
#21986984   $24ea: bne $24ea     A: $15 X: $ff Y: $ff SP: $ff F: $73 .V..CZ  $00 $00 $bd $ad $01 $99 $00 $00
#21986985   $24ec: lda #$f0      A: $f0 X: $ff Y: $ff SP: $ff F: $f1 NV..C.  $00 $00 $bd $ad $01 $99 $00 $00
#21986986   $24ee: sta $0202     A: $f0 X: $ff Y: $ff SP: $ff F: $f1 NV..C.  $00 $00 $bd $ad $01 $99 $00 $00
#21986987   $24f1: stp           A: $f0 X: $ff Y: $ff SP: $ff F: $f1 NV..C.  $00 $00 $bd $ad $01 $99 $00 $00

Test results:                "programs\65C02_extended_opcodes_test.hex"

  Instructions executed:     21.986987 M
  Total clock cycles:        66.905005 M

  Elapsed time:              0.5710 sec
  Average clock rate:        117.1716 MHz
  Average instruction rate:  38.5061 MIPS
  Average clocks/instruction 3.0429

  Test completed:            PASSED

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