Thanks. I and my students will look into it.
Which version of the circuit is the most recent one, the one currently at GitHub (shown below left) or the one described in the documentation (Breaking NES Book 6502 Core Rev. B4) (shown below right)?

Both are an approximation of what is actually there.
Logisim does not support bidirectional connections, which are used in large numbers at the bottom of the processor (buses).

The one in the book contains no special "hacks" to handle bus conflicts.

You need to figure out on your own how best to simulate bidirectional connections in your program if it does not support inOut entities (in Verilog terms).

It is best to read carefully what is written on our wiki, I think all questions will disappear naturally

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6502 addict

@org, okay, thanks!

First of all, great work!

I stumbled upon a few things while recreating the schematic in KiCad/eeschema which I thought would be nice to share.

First, I noticed that the output databus is latched at the end of phase 1. That's apparently how Logisim RAM works. This is not the same as real hardware where the transaction takes place during phase 2 and ends when R/W goes high again.

Secondly, I noticed that the transfer of SB to AC on PHI2 only seems to work because of a hazard that occurs in Logisim. SB/AC and PHI2 are not supposed to ever be high at the same time, but there is a small window when PHI2 goes high before SB/AC goes low again.



This is a side effect of Logisim's simulation. Other simulations I ran (LCC, another ED simulation, and Verilator) failed to latch SB into AC. I fixed this by latching on SB/AC directly.

Thirdly, the BCD correction does not work. I traced it back to the following wrong connection:



/carry3 connects after the AND port. After that, the full 6502 Dormann test passes!