MCL65+

[MicroCoreLabs]

Hi,

I thought I would share a project that I am currently working on. It is called the MCL65+ and is a 6502 emulator running on a Teensy 4.1. The goal is to build a board which can be used as a drop-in replacement for the 6502 which can run both as cycle accurate and accelerated modes. The code is open-source and compiles using the Arduino IDE, and the board is inexpensive ($5 for quantity 10) and uses through-hole components. It was designed to be accessible to anyone to wants to create their own builds!

Here is my blog: https://microcorelabs.wordpress.com

Thanks,
-Ted Fried

[BigEd]

Great! That's got everything... (I even have a Teensy, but not a 4.1, as yet.)

[MicroCoreLabs]

Well, it has some possibilities at least!

Thanks,
-Ted

[BigEd]

One thing @revaldinho found with an earlier Teensy is that the I/Os are not wired up in a very nice grouping, so reading or writing the micro's bus takes some shifting and masking. That takes up clock cycles - but at 600MHz, possibly no problem at all. Maybe you can even stick to C code and still meet the deadlines... do let us know how you get on.

[MicroCoreLabs]

The same seems to be true for the Teensy 4.x boards if you need to achieve a fast parallel bus... Performing sixteen address bit writes using digitalWriteFast() was not fast enough to make bus timing, so I ended up performing read-modify-writes directly to three of the CPU's GPIO registers. It was a bit more complex due to the pin assignments which I chose to optimize the board layout rather than optimal register/GPIO mapping.

[BigEd]

Meeting timing at 1MHz - that's a milestone! Well done.

[MicroCoreLabs]

The boards and components arrived, so I assembled one today, plugged it into my VIC20, and got some good results!

Here's the update on my blog: https://microcorelabs.wordpress.com/202 ... n-a-vic20/

I am happy to say that it's possible to both emulate a 6502 as well as its bus interface.. at least at 1Mhz!

Some fun next steps will be to use the Teensy's huge memory to expand the VIC20's RAM to the max and to import some cartridges.
It would also be amusing to execute code from some memory ranges which are not limited to the 6502's 1Mhz bus but run at the mirocontroller's 600Mhz clock speed!

I will upload the project to GitHub shortly.

Thanks,
-Ted

[rpiguy2]

Do you have any idea how fast you can push the emulated 6502 clock speed and maintain accuracy on the 6502 bus?

My guess would be about 4-5mhz, which is still very fast.

I think it would be interesting to modify this project to emulate the 6510 in the Commodore 64. The VIC can let the processor know when it is safe to run at full speed when drawing the screen borders.

https://sites.google.com/site/h2obsessi ... mhz-border

It should also trivial to simulate a GEORAM expansion with the internal RAM of the Teensy. The possibilities are exciting.

[BigEd]

(Is the 6502 model cycle accurate in the sense, say, that a taken branch will take 3 cycles?)

[MicroCoreLabs]

Quote:

Do you have any idea how fast you can push the emulated 6502 clock speed and maintain accuracy on the 6502 bus?

My guess would be about 4-5mhz, which is still very fast.

I think it would be interesting to modify this project to emulate the 6510 in the Commodore 64. The VIC can let the processor know when it is safe to run at full speed when drawing the screen borders.

https://sites.google.com/site/h2obsessi ... mhz-border

It should also trivial to simulate a GEORAM expansion with the internal RAM of the Teensy. The possibilities are exciting.

The limiting factor is the clock to address propagation time because all 16 address lines cannot be generated simultaneously with the Teensy 4.1. Also, the address cannot be generated until the previous instruction has been decoded which adds to the propagation time. I think this would limit the bus speed to the 1-2Mhz range using an off-the-shelf Teensy.

I think this project could easily be ported to emulate a 6510. It would just require a different PCB pinout and support for the new signals. I chose the 6502 pinout because I have a VIC20 and an Apple II+ that I can try it on.

[MicroCoreLabs]

Quote:

(Is the 6502 model cycle accurate in the sense, say, that a taken branch will take 3 cycles?)

Yes I tried to make the MCL65+ cycle accurate and included the extra clocks, fetches, and double write-backs as well as most of the undocumented opcodes. It's all simple C code, so in theory it can be massaged into a cycle-exact emulator. (Will probably need this forum's help to achieve that!).

I need to upload the code to GitHub, but I have less then two hours of uptime and I want to clean it up before posting.

One challenge I encountered was that the simple 10 a=a+1, 20 print a, 30 goto 10 program randomly stops due to a "Syntax Error on line 10". The VIC20 does not crash, it simply stops the program with this error.. and it does so randomly... sometimes after 200 iterations.. sometimes 1000... If I just print "Hello World" in this tight loop it never fails...

I believe it is caused by the "math". (happens if I do a=a+1 or a=a-1), and possibly something related to the flags and/or the stack and interrupts... I suspect that while the code is running an interrupt occurs which pushes the flags recently generated by the math, but the flags are not restored correctly upon RTI... This is just a guess!

[BigEd]

Mmm, that's tricky. Dave/hoglet's 6502 protocol analyser might be of use - it reads a trace and models the 6502 behaviour. And then there's Klaus' test suite too, if you haven't already run that.

[rpiguy2]

MicroCoreLabs wrote:

The limiting factor is the clock to address propagation time because all 16 address lines cannot be generated simultaneously with the Teensy 4.1. Also, the address cannot be generated until the previous instruction has been decoded which adds to the propagation time. I think this would limit the bus speed to the 1-2Mhz range using an off-the-shelf Teensy.

I think this project could easily be ported to emulate a 6510. It would just require a different PCB pinout and support for the new signals. I chose the 6502 pinout because I have a VIC20 and an Apple II+ that I can try it on.

I did not know that.

[MicroCoreLabs]

Quote:

Mmm, that's tricky. Dave/hoglet's 6502 protocol analyser might be of use - it reads a trace and models the 6502 behaviour. And then there's Klaus' test suite too, if you haven't already run that.

Found it... In the interrupt processing routine I was pushing PCH and then (PCL-1)... When the (-1) causes a borrow I was pushing a bad PCH...

[MicroCoreLabs]

I mirrored the 6502's address range from 0x2000 to 0x8000 in the MCL65+ to increase the computer's memory. While read and write cycles are generated on the 6502's bus, the data for this range is handled using an internal memory array.

Is 28159 the maximum that the VIC20 supports, or can the expansion range from 0x0400 be harvested as well?