I've been using visual6502's ARM1 to better understand how CPUs work, and so far it has been excellent. I've been digging through the code and I'm a bit confused about what a node represents? A node has 1 or more transistors, a "state", and a flag indicating that it represents a flip flop, yes?

Am I to understand that a node in this code represents a logic gate?

And what is the meaning of state? And what is the difference between gates and c1c2s?

Thank you in advance. This is by far the coolest way to learn about the internals of computers.

Hello, and welcome!


Great to hear it!


A node is a collection of electrically connected conductors which necessarily sit at the same voltage. So, bits of metal, of polysilicon, the contacts between them, and including any source, drain or gate parts of transistors.

It might be helpful to say that nodes are separated by transistors, and transistors are connected by nodes.

I'm not sure about the 'flag' part of your description... let's look at some source files of the visualARM:
http://www.visual6502.org/sim/varm/ffdefs.js
http://www.visual6502.org/sim/varm/nodenames.js
http://www.visual6502.org/sim/varm/transdefs.js
http://www.visual6502.org/sim/varm/displaynames.js

So, yes, it turns out for the visualARM, a CMOS design, we needed some extra annotation to help simulate the flip flops. (Whereas in the visual6502 and visual6800, which are NMOS designs, we needed some annotation to indicate the pull-up transistors.)

As far as I can tell with a quick look: it looks like the flip-flops are constructed in the ARM1 using cross-coupled inverters, which are written to by overdriving the bit lines. To the simulator, that looks like a 1 fighting a 0 and it needs to have some heuristic for which value will win. By annotating the flip-flops, we could use the heuristic that such a conflict on a bitline is intended to flip the flop.


Not really. But the output of a logic gate will always be a node, and usually a node will be the output of exactly one logic gate. There are also interior nodes of logic gates, for example when two pulldown transistors in series are part of a NAND gate, there is a node between the two.


By state, I think we will mean whether the node is at a high voltage or a low voltage, which is to say a logic 1 or a logic 0. In general, a simulator might model several possible voltages or several strengths of logic level, but it turns out in the visual simulators, we only needed to model high or low: one bit.


A transistor has three terminals, conventionally called source, drain, and gate. In the case of MOS transistors in digital chips, the source and drain are physically indistinguishable, and the structure is symmetrical: the gate sits over the channel, and the channel sits between the source and drain. If the gate is at a high voltage (for an NMOS transistor) the channel conducts and current will flow to equalise the source and drain voltages. (For a PMOS transistor the channel conducts when the gate is at a low voltage.)

So, the gates in the JS are the gates, and the c1c2s - I think - are the list of sources and drains of the various transistors connected to a node. I think this structure is different in visualARM compared to the two previous, NMOS-only, simulators. I could be wrong.


You're welcome - I feel the same way!