ScottySR wrote:
The block diagram seems to have the timing signal named as "T1X" between "T1" and "T2". Is this timing state somehow special? I'm assuming this is the same state as the "T0+T1" state that was mentioned.
Might be worth reading
this page on the visual6502 wiki. My feeling is that you have to go quite deep to put together the various descriptions and notations of the timing states which different people at different times have put together. You can also
search this forum for T1x, but you'll have some reading to do!
Quote:
The last thing I wanted to ask for now is related to the clock of the CPU. There seems to be two outputs, ø1 and ø2. According to one CPU clock diagram ø1 is high when the clock generates a high signal and ø2 when the signal is low (basically inverted output). Is this how the 6502 CPU clock works? More importantly, what purpose does the ø2 serve in the functionality of the CPU?
Not directly answering your question, but:
- phi2 as an output (pin 39) tracks the phi0 input (pin 37), with a slight delay.
- phi1 (pin 3) is very rarely used.
- there is some subtlety as to whether it's best, for the rest of the system design, to use the phi2 as it is fed into the 6502 or the version which comes out of the 6502.
- internally to the chip, phi1 and phi2 signals are non-overlapping, which isn't quite the same as being inverses of one another.
So, within the chip, the alternation of phi1 and phi2 is what allows data to be shuffled without loss from one transparent latch to the next. Two transparent latches make a flop, but unlike a flop it's possible to have logic in between the master and slave.
For most purposes, we can just use phi2 as a reference. Inside the chip, some things happen during not-phi2, the first half of a cycle, and some things happen during phi2, the second half. Mostly, actions are spread over two adjacent phases, either phi1 and phi2, or phi2 and phi1.
Outside the chip, all events are relative to the falling edge of phi2. The rising edge of phi2 is a convenient signal but does not define the timing of any external event for the 6502. (It is used by the '816 to multiplex the high byte of the 24 bit address onto the databus.) It is conventional, and convenient, to use phi2 as a mask to distinguish the early part of a cycle, where the address and control lines are changing, from the later part of a cycle, when the address and control lines are stable, and a write can be committed to exactly the right location. (It's also possible to use a different reference, if for example there's a 6x or 8x clock available in the system, or indeed to use logic delays, for the bold and intrepid.)