So, I'm having trouble understanding what "Precharge MOSFETs" means from the block diagram (https://projects.ncsu.edu/wcae/WCAE1/hanson.pdf).

I'm trying to understand physically how the 6502 handles a BRK instruction. I get how it works logically, but I'm confused about how it orchestrates things on the hardware-level. The reason I am confused by this operation is that there appears to be some combination of Precharge and Drain MOSFETs going on to construct the high and low address bytes (of significance is 0/ADL0, 0/ADL1, 0/ADL2). That's fine, but we don't seem to sample ABL until phi1 - so how can some changes we've made on ADL during phi2 still be lingering on the wire during phi1? And furthermore, why doesn't this cause problems when we put legitimate ADL information on the bus during phi1 of regular instruction execution (say, going to fetch the next byte after an INC) since it appears from the block diagram that the "Precharge" takes place every phi2. Wouldn't we just mess up our own signal if it really sticks around?

Looking around on the visual simulator, I can find all the important bits...

AB0 (for example): http://www.visual6502.org/JSSim/expert.html?nosim=t&panx=78.8&pany=369.6&zoom=6.2
Gates and drains for signal propagation from ADL0 to AB0: http://www.visual6502.org/JSSim/expert.html?nosim=t&panx=110.1&pany=352.2&zoom=12.4
Nearby, you can see the important DPC signals for 0/ADL0, 0/ADL1, 0/ADL2 for diffusing the wire to ground (connected at the top-left of the ASL0->AB0 propagation logic)

But I'm having trouble finding where the wire goes high for "Precharge MOSFETs", and I'm also having trouble understanding how it stays high during the first clock phase, since there is no data for BRK's constructed interrupt vector address stored away in any registers (AFAIK). The only thing I can think of is the wire is high due to capacitance, and perhaps since BRK is ongoing something doesn't diffuse it to ground somewhere - but this is just a guess, and I can't seem to find where that may be, or if that theory even makes sense.

Regardless, at this point I'm a bit lost - can anyone help me understand what is going on here?

I didn't read that article nor played with visual6502. But I know a MOSFET can keep its state for a lengthy period due to the intrinsic capacitance between Gate and Drain or Source. Power MOSFETs can stay "ON" for hours. Second I know that the NMOS 6502 requires a certain minimum clock frequency (some 100 KHz). This may come together if the designers uses a technique (dis)charging a MOSFET and then leave it "floating" for say a half clock cycle. The MOSFET doesn't change its state during this time for sure.

Indeed, the chip doesn't work below a certain speed, and the reason is leakage. There are very many places on the chip where charge is held on a node for a phase or maybe as long as a cycle. For the chip to work, the node needs to be higher than a threshold, and is charged somewhat above that threshold, which gives some robustness against noise and leakage.

The nature of MOSFETs is that the gate acts as a capacitor - it's very much a plate with a thin oxide separating it from the bulk silicon below, which is where the channel forms. There are other capacitances too: every wire is a plate, over somewhat thicker oxide, and the edge of every active area (aka diffusion) is a reverse-biased diode. The gates and diodes have a capacitance which varies with voltage, but that's not too important here.

As it happens, visual6502 can work without modelling any of the analogue nature of charge, but it must model the stickiness of a node's logic level when it's not driven. And that happens more or less by default, because variables in JavaScript don't leak!

I think there was need for just a little care in how the nodes are updated during each phase, to ensure the charge-storage model is good enough. I think, for example, that decrement and increment instructions use the precharged state to provide an FF into the ALU. Similarly, all the high bits of the six vector addresses are precharged state: signals like 0/ADL1 are conditional pulldowns, which form the low bits.

Having said all that... do we need a picture, or better explanation? It would be quite good perhaps to have a page on the visual6502 wiki to address questions like these - they are good questions!

(GaBuZoMeu: I would not say so much that a MOSFET stores its on or off state, rather that the gate stores charge which causes its voltage to stay high or low, such that the channel remains conductive or non-conductive.)

I wanted to avoid a too lengthy explanation - perhaps I said it a bit too simple

No problem for me! My sentence is very far from simple... :unhappy face:

BTW, here are two of the precharge transistors for ADL:
http://www.visual6502.org/JSSim/expert. ... &zoom=12.4

Here's idb0's precharge transistor:
http://www.visual6502.org/JSSim/expert. ... &zoom=12.4

and here's idb precharged to FF to perform an INX:
http://www.visual6502.org/JSSim/expert. ... l&steps=20

I'll admit to knowing rather less about dynamic logic than the static variety. But it strikes me as being a way to reduce power consumption (in an NMOS device) by not having continuous current paths. So you pull stuff up on one clock phase, selectively pull it down again on the next, and the stuff that wasn't pulled down stays up. It undoubtedly goes hand-in-hand with the 6502's quadrature clock.

Yes, that's the gist of it, alright. But AIUI the approach was adopted not to save power but because of inadequacies of the on-chip transistors they were able to make in those days. (Maybe Ed or someone can elaborate on the exact details.) If the result of a logic "decision" dictated that a circuit node needed to be pulled down, that was something that could be accomplished promptly. But pulling a circuit node up was not so quickly and easily done. So, instead they place the nodes in a high state as a default, well before the decision is made -- then, as you say, selectively pull the appropriate ones down. Quite a clever workaround!

BTW the 6809 uses two clocks sometimes described as quadrature, but 6500 family chips do not. The 6809 uses two clocks signals, each nominally 50% duty cycle, with one shifted 90 degrees so it partially overlaps with the other. Thus there are basically four states (not two, as with 6500). And recently I happened to learn the TMS9900 CPU also has four possible clock states, but it's done with four non-overlapping 25% clock signals on four separate clock-input pins!

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Indeed, I don't think there's anything special there to save power. The general story in NMOS logic is that the depletion-mode pullups are always conducting, so every logic zero is causing current to flow between the rails - on average, that's half the logic gates on the chip. (Hence the great improvement when we moved to CMOS.)

It's even worse with the Special Bus, which is precharged in phi2 but may also be driven during phi2: probably no useful logic level will result, but probably the value on the bus is not used in phi2 so no logical misbehaviour. See for example this sim.

There's some info in the thread circuit netlist for 6502 in spice format which relates to this.

There are several ways a node can be high:
- charge storage, from something which happened recently.
- through one or more pass transistors, in which case high is about 4V or a little less, because of the threshold drop.
- from a logic gate with a depletion mode pullup, in which case high is 5V.
- by a precharge transistor, which is again only pulling up to 4V.

In the 6502, to perform a LDX immediate, such as in cycle6 of the sim above, the value which has been loaded into the data latches (idl) passes over the internal databus (idb) to the special bus. That's a long way, and through several weak pass transistors, so would be somewhat slow to transmit a zero and even slower to transmit a 1. By precharging the bus, it only needs to transmit a zero, and so avoids being too slow. That is, in this case, precharging is a timing fix.

But as we noted before, precharging is also used to create useful constants, so if it's not modelled correctly, the simulation won't entirely work.

Ah, I knew I'd seen a quadrature clock in use somewhere (besides the modern HC08 microcontrollers, which keep it internal). The TMS9900's bizarre clock is I think also used on other TMS series chips, such as the 34010 (intended as a graphics processor, in the days before 3D shaders).

Anyway, CMOS is Just Better, isn't it?

Well, CMOS is significantly less dense, and needs a more complex process. So, pros and cons. The RCA 1802 is very interesting though... but this is off topic.

The 6502's on-chip clock is I think best described as a non-overlapping clock.

Thanks, everyone! This is all really useful information.

Taking what you all have said into account, I'm watching the AB1 pin and I can see some of the engineering you were discussing at work here - specifically, I think I see how the pin being low or high allows current to flow to either dissipate or keep the charge. The precharge transistor for bringing the nodes high makes sense as well, as it is controlled directly by cclk, which is what I would expect. Honestly, I'm still very much a beginner, so I'm really trying to wrap my head around some of these intricacies.

My error was that I was assuming during phi1 that the wire was immediately connected to the pin, gated by ADL/ABL for instance, but I suppose that is a little naive - looking at the simulator, I can see that it is much more complicated than that - but has the logical effect of:

1. Maintaining the phi1 old value on the pins during phi2.
2. Bringing the wires hot for phi2 in preparation to dissipate unneeded charges for the next value.
3. Low values will end up with the result of allowing charges to dissipate from phi2, producing the right "value".

Hmm, I'm unsure - I think it depends on how approachable you want this information to be. I'm a software engineer, so I can reason about logic very well, but I'm a complete newbie when it comes to hardware. I am researching before I ask questions; I've watched many beginners videos on Electrical Engineering, and explanations for how MOSFETs work and what they are - but I think some of these topics are pretty advanced for me and are just new things I need to learn as I go.

I did read different parts of the WIKI trying to find information about MOSFETs, and read on there first about wires holding values through capacitance (as well as some videos I've watched talking about this) - but this is still a very new topic to me, so with that there is some uncertainty around me just accepting something as truth. Possibly things could be made better with a WIKI page on MOSFETs and tips about some of the tricks the 6502 engineers used to store and dissipate charge.

Learning what you all have said here, the precharge phase is very important, much more than I thought - and I'm a little surprised I wasn't able to find anything concrete on it. I think people could definitely gain a deeper understanding of the hardware with a good write-up. That being said, I also understand my question is very special-case; so this is just my feedback on the matter.

I really appreciate all the help!

I'd be happy to set up a wiki account for you, if that's not already automatic - in some ways, the best person to start writing an explanation is someone who has just tackled the question themselves. As a wiki, anyone could then refine that first effort. It would probably be good even just to list some useful pages and videos you've found.

Most people, I think, would be more likely to approach visual6502 with a programming background rather than an electronics background - just because that's the more common case in our world today. Even if not most, then a solid proportion. It's worth striving to write explanations which work in this case. And of course, we were all beginners once.

(BTW, not meaning to be passive-aggressive about the wiki - this is a good thread and I might try to write it up as a wiki page myself, eventually, if no-one else does.)

Yeah, I wouldn't mind taking a stab at writing a wiki page on this - it might take me some time though. I'm still learning things about the 6502, and I only get time to really look at this stuff on the weekend in any kind of depth. I'll take a look at doing this over the next week or two. I also don't believe it is automated, as I tried to log in and was met with "There is no user by the name 'TrentoReedo'", it says to PM you to get this set up - so I'll do that just so it's in your inbox.