So we know that on NMOS 6502s, a read-modify-write instruction was implemented using one read from the effective address, and two writes (one unmodified, one modified). On CMOS, this was changed so that two reads and one write are performed.

Can anyone confirm that, on CMOS 6502s, the operation is performed on the value from the first read rather than the second? It seems fairly clear that this would be the case, as during the second read cycle, the ALU should be processing what was read in the first read cycle, but you can never be too sure. There are some gruesome cases where this could matter, e.g. RMW on a 6522 timer.

Thanks!

I agree, it must be true - an experiment on a BBC Master, reading the timer as you suggest, would prove it.

Thanks a lot Ed, helpful as ever!

Certainly there are cases where this could matter. But the amount of doubt about the outcome is awfully small! And running a test might actually be quite awkward to arrange, unless you can single-step or have a logic analyzer to capture what happens.

What I would do myself, in light of how very small the doubt is, would be to trust that the behavior is as presumed, and go ahead and write whatever time-critical code you require. IMO there's very little risk you'll be forced to subsequently tweak that code because the presumption was wrong.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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