Three things to say:
First: if the designers would have built the envelope generator according to the school books,
maybe it would have taken 50% more space on the silicon.
Second: had no time to check what exactly happens in which clock cycle,
so please don't take the cycle counts in my block diagram too serious, sorry.
Third: the SID uses a LFSR (linear feedback shift register) as a noise generator.
While the binary sequence generated by a LFSR looks somewhat random to the human eye,
it certainly _is_ a predictable sequence, so the designers used two LFSRs as counters.
Block diagram of the envelope generator:
Attachment:
envelope_block.png [ 295.98 KiB | Viewed 8753 times ]
We now initiate the envelope generator by setting 'Gate' to 1 to start 'Attack phase'.We have a 15 bit LFSR counter running at PHI2 speed, feeding a PLA with its outputs.
The PLA compares the LFSR with a value according to the registers: 'Attack', 'Decay' and 'Release'.
(Register is selected by the 'envelope control block.)
At the moment, it's 'Attack' register.
If the LFSR has reached a certain value, it is set to $7FF,
(since $000 would freeze the LFSR counter, all bits are set to start a new counting sequence)
and during 'Attack phase' the 8 bit envelope counter (which feeds the envelope DAC that sets
the amplitude of the analog waveform signal from the oscillator block) "increments" by one step.
So the 15 bit LFSR counter is in fact a predivider, that divides down PHI2.
Example: 'Attack phase', 'attack register' is $0, 2.048ms Attack time.
If PHI2 is 1MHz (1us clock cycle) and the LFSR15 counter divides it by 8,
the envelope DAC counter "increments" at 1MHz/8, that's 125khz (8us clock cycle).
Since the envelope DAC counter is 8 bit, "incrementing" it from $00 to $FF takes 256 clock cycles
8us each, that's 8us*256=2048us... or 2.048ms.
After the envelope DAC counter has reached $FF, 'Attack phase' ends and 'Decay phase' starts.From here, the envelope DAC counter starts "decrementing" back toward $00.
The evil thing here is, that it doesn't count down in a
linear fashion like when counting up.
Depending on the value in the envelope DAC counter, count frequency is changed to make the amplitude drop
nonlinear, in other words to make it look somewhat "exponential".
For this, we have another 5 bit LFSR counter feeding another little PLA.
When the envelope DAC counter has reached "Sustain level" while counting down,
'Decay phase' ends and 'Sustain phase' starts, in which the counter does nothing.
When setting 'Gate' to 0, 'Sustain phase' ends and 'Release phase' starts.The envelope DAC counter just continues with "decrementing" down to $00 in nonlinear fashion.
When the envelope DAC counter has reached $00, 'Release phase' ends and the counter stops counting, waiting for 'Gate' to go 1 again.
;---
This was the simplified version, of course.
In the text above, I wrote "incrementing" or "decrementing" the envelope DAC counter.
Actually, the counter really is an up\down counter, but it usually counts up.
The counter has XOR gates at the outputs, and inverting the outputs of an up_counter
makes it _look_ like a down_counter.
We are getting there later, just don't get confused about this now...
;---
Edit:
After looking at the picture again in 2018, I think I have spotted some errors.
The XOR gate at the LFSR5 counter probably should connect to the Q2 output of the shift register instead of the /Q2 output,
and I'm not sure about the polarity of the release_reset signal.