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PostPosted: Sun Aug 14, 2016 4:11 pm 
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Hi,

I was just thinking, this might be of interest to some of you:

https://github.com/GBuella/chipemu

It is a rewrite of https://github.com/mist64/perfect6502 ( which is in turn a rewrite of the visual6502 js code )


Cheers


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PostPosted: Sun Aug 14, 2016 4:28 pm 
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Joined: Thu Dec 11, 2008 1:28 pm
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Welcome, Tej, and thanks for the pointer! I'd love to see someone tackle a dynamic-compiled version of this chip simulator - notice that it will evaluate the same sets of transistors many times over for every clock cycle, which it does by looking through data structures which never change. There's an opportunity there to compile native code which encapsulates the transistor network. (Maybe, but not necessarily, by providing a function for each logical grouping of transistors.)


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PostPosted: Sun Aug 14, 2016 4:36 pm 
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Well, the connections do change between the nodes, and there is not much else in the data structures. But generating C source code is really not rocket science, so it might be worth a try. One just needs a few free weekends for it.


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PostPosted: Mon Aug 15, 2016 1:28 pm 
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Nice, I will give it a spin!
Are there any other changes or it's just a language conversion? And what about the performance?


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PostPosted: Tue Aug 16, 2016 7:43 am 
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drfiemost wrote:
Are there any other changes or it's just a language conversion?

Well, there are a lot of little changes. The data structures are bit more compact. It is supposed to be easy to add other netlists, I just didn't have time for that. It should be easy to add other emulated machines. Currently I wrote a tiny Commodore like kernel, and ./testbench can work as a C=64, or VIC20.
Mainly, it should be easy to use it as a standalone library.

drfiemost wrote:
And what about the performance?

The original goal was to make it a lot faster, while also learning some C++. I tried to get things as compact as possible, to see what happens if most stuff fit into L1 cache. As I recall, I managed to get it about 10% faster, then gave up on it.
Also, I'm not familiar with IC design, it is the first netlist I'v seen in my life, so that might be a thing holding it back. It took many weeks to "almost understand" how the simulation works, based on the source codes.


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