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ariejan
PostPosted: Fri Aug 15, 2014 7:17 pm 
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Location: Son en Breugel, NL
I've written an emulator in Go. Yes, I'll release it as open source.

However, I'm now running Klaus Dormann's test file and I've already fixed a number of issues. Now I've run into one I can't wrap my head around. Maybe someone can help me figure this out.

I've used the files available from github, the corresponding listing to the binary I used can be found here: https://github.com/Klaus2m5/6502_65C02_ ... .lst#L3932

The issue seems that a CMP does not give the right result, but I don't know why.

The following is the debugging output starting a `0x0EDC`, which according to the listing tests "LDY / STY - zp,x / abs,x". It seems to run through this part a first time okay, but then does it a second time and fails.

Can someone point me into the right direction to finding the issue at hand? Thanks so much!

The `~~~` lines are instructions read in the format: `~~~ PC: OPCODE - OPCODE OPERAND [ADDRESS MODE] {CYCLES}`

Code:
>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x11   0x00   0xFF   0xFF   0x0EDC  01111101

~~~ 0x0EDC: 0xA2 - LDX 0x03 [immediate] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x11   0x03   0xFF   0xFF   0x0EDE  01111101

~~~ 0x0EDE: 0xA9 - LDA 0x00 [immediate] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x03   0xFF   0xFF   0x0EE0  01111111

~~~ 0x0EE0: 0x48 - PHA [implied] {3}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x03   0xFF   0xFE   0x0EE1  01111111

~~~ 0x0EE1: 0x28 - PLP [implied] {4}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x03   0xFF   0xFF   0x0EE2  00100000

~~~ 0x0EE2: 0xB4 - LDY 0x13 [zeropageY] {4}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x03   0x00   0xFF   0x0EE4  00100010

~~~ 0x0EE4: 0x08 - PHP [implied] {3}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x03   0x00   0xFE   0x0EE5  00100010

~~~ 0x0EE5: 0x98 - TYA [implied] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x03   0x00   0xFE   0x0EE6  00100010

~~~ 0x0EE6: 0x49 - EOR 0xC3 [immediate] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0xC3   0x03   0x00   0xFE   0x0EE8  10100000

~~~ 0x0EE8: 0x28 - PLP [implied] {4}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0xC3   0x03   0x00   0xFF   0x0EE9  00110010

~~~ 0x0EE9: 0x9D - STA 0x0203 [absoluteX] {5}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0xC3   0x03   0x00   0xFF   0x0EEC  00110010

~~~ 0x0EEC: 0x08 - PHP [implied] {3}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0xC3   0x03   0x00   0xFE   0x0EED  00110010

~~~ 0x0EED: 0x49 - EOR 0xC3 [immediate] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x03   0x00   0xFE   0x0EEF  00110010

~~~ 0x0EEF: 0xDD - CMP 0x0208 [absoluteX] {4}

CMP A: 0x00 V: 0x00
>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x03   0x00   0xFE   0x0EF2  00110011

~~~ 0x0EF2: 0xD0 - BNE 0xFE [relative] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x03   0x00   0xFE   0x0EF4  00110011

~~~ 0x0EF4: 0x68 - PLA [implied] {4}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x32   0x03   0x00   0xFF   0x0EF5  00110001

~~~ 0x0EF5: 0x49 - EOR 0x30 [immediate] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x02   0x03   0x00   0xFF   0x0EF7  00110001

~~~ 0x0EF7: 0xDD - CMP 0x020D [absoluteX] {4}

CMP A: 0x02 V: 0x02
>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x02   0x03   0x00   0xFF   0x0EFA  00110011

~~~ 0x0EFA: 0xD0 - BNE 0xFE [relative] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x02   0x03   0x00   0xFF   0x0EFC  00110011

~~~ 0x0EFC: 0xCA - DEX [implied] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x02   0x02   0x00   0xFF   0x0EFD  00110001

~~~ 0x0EFD: 0x10 - BPL 0xDF [relative] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x02   0x02   0x00   0xFF   0x0EDE  00110001

~~~ 0x0EDE: 0xA9 - LDA 0x00 [immediate] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x02   0x00   0xFF   0x0EE0  00110011

~~~ 0x0EE0: 0x48 - PHA [implied] {3}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x02   0x00   0xFE   0x0EE1  00110011

~~~ 0x0EE1: 0x28 - PLP [implied] {4}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x02   0x00   0xFF   0x0EE2  00100000

~~~ 0x0EE2: 0xB4 - LDY 0x13 [zeropageY] {4}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x02   0xC3   0xFF   0x0EE4  10100000

~~~ 0x0EE4: 0x08 - PHP [implied] {3}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x02   0xC3   0xFE   0x0EE5  10100000

~~~ 0x0EE5: 0x98 - TYA [implied] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0xC3   0x02   0xC3   0xFE   0x0EE6  10100000

~~~ 0x0EE6: 0x49 - EOR 0xC3 [immediate] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x02   0xC3   0xFE   0x0EE8  00100010

~~~ 0x0EE8: 0x28 - PLP [implied] {4}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x02   0xC3   0xFF   0x0EE9  10110000

~~~ 0x0EE9: 0x9D - STA 0x0203 [absoluteX] {5}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x02   0xC3   0xFF   0x0EEC  10110000

~~~ 0x0EEC: 0x08 - PHP [implied] {3}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0x00   0x02   0xC3   0xFE   0x0EED  10110000

~~~ 0x0EED: 0x49 - EOR 0xC3 [immediate] {2}

>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0xC3   0x02   0xC3   0xFE   0x0EEF  10110000

~~~ 0x0EEF: 0xDD - CMP 0x0208 [absoluteX] {4}

CMP A: 0xC3 V: 0x41
>>> CPU [  A ] [  X ] [  Y ] [ SP ] [  PC  ] NVxBDIZC
>>>      0xC3   0x02   0xC3   0xFE   0x0EF2  10110001

~~~ 0x0EF2: 0xD0 - BNE 0xFE [relative] {2}

--- FAIL: TestKlausDormann6502
panic: Looping PC detected. We've hit a failing Klaus Dormann test.

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BigEd
PostPosted: Fri Aug 15, 2014 7:34 pm 
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Could be your B4 opcode is wrong:
0ee2 : b413 ldy zp1,x
~~~ 0x0EE2: 0xB4 - LDY 0x13 [zeropageY] {4}
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MichaelM
PostPosted: Fri Aug 15, 2014 9:18 pm 
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I agree with BigEd. His statement may not be clear enough.

The $B4 instruction is a LDY instruction, except that it appears that you are interpreting it as post-indexed zero page direct instruction, i.e. LDY zp,Y, which is not a valid instruction. The indexed zero page direct addressing mode of the LDY and LDX instructions cannot use the destination register as the index register. IOW, the index register for these instructions is the opposite of the destination register: LDX zp,Y and/or LDY zp,X.

Edit: the same restriction applies to the indexed absolute addressing mode of these instructions: LDX abs,Y and LDY abs,X. Furthermore, this restriction on the index register also holds for the STX zp,Y and STY zp,X instructions. (There isn't a STX abs,Y or a STY abs,X instruction.)

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ariejan
PostPosted: Sat Aug 16, 2014 7:10 am 
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Location: Son en Breugel, NL
Hey, thanks!

I must have mis-copy-pasted that from LDX. My STY commands are in good order. Fixing the addressing mode fixed this issue.

Now, on to the next!

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BigEd
PostPosted: Sat Aug 16, 2014 9:11 am 
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Sorry for my super-terse "assistance" - thanks Michael for taking the trouble to elaborate. And congratulations ariejan on your emulator!

It might be worth a word or two about the B bit in the P register. There are two approaches: one is to arrange that it is always 1, and the other is to arrange that it is always read as a 1. There's barely any practical difference, but if you're taking the second approach you also need to fiddle your monitor status display. I think it's more natural to set it to 1 at reset time, and set it again during any RTI or PLP. When you take an IRQ, you don't change the B bit in P, but you do modify the P value which is pushed to the stack. I think this approach is closer to what the chip actually does too, as seen in visual6502.

Cheers
Ed


Last edited by BigEd on Sat Aug 16, 2014 2:17 pm, edited 2 times in total.

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ariejan
PostPosted: Sat Aug 16, 2014 9:15 am 
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Hey BigEd, no worries about your reply.

I've got the full test suite running now :-)

Code: https://github.com/ariejan/i6502
Latest test output: https://travis-ci.org/ariejan/i6502

Next actions:

* 65C02 Support
* 6522 and 6551 emulation
* Actual webpage, with web sockets to connect to your own i6502 instance ;-)
* Convert i6502 emulator into a working hardware design.
* ???
* Profit!

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BigEd
PostPosted: Mon Aug 18, 2014 10:30 am 
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(That travis-ci looks quite handy - a free continuous integration service hooked up to your github repo.)
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ariejan
PostPosted: Mon Aug 18, 2014 10:39 am 
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BigEd wrote:
(That travis-ci looks quite handy - a free continuous integration service hooked up to your github repo.)


Oh, it is. Github also has Pull Requests (if you don't know them, they are branches of your code with changes or new features). Travis also tests these and reports if the code is safe to merge (in terms of passing tests).

Note that travis runs my own tests *and* Klaus Dormann's test rom :-)

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