Request for verification:
Tried to "convert" some part of the VIC-II related VHDL from FPGA64 into sort of a "TTL styled schematic".
My intention was to have a "starting point" for what the logic for something more or less compatible to a VIC-II
might look like just in case we might be going to need this for the C74 project later.
Background is, that from the microscopic VIC-II chip pictures and with the tools and skills I happen to have
I don't have much of a chance of reverse engineering the VIC-II silicon... and that's what had brought me to FPGA64.
Any thoughts about compacting/optimizing this stuff for a TTL implementation better should go into a different thread,
same thing for "low level TTL related timing issues" and "system integration".
Don't have much time for this at hand right now, but maybe in December 2017 or so.
Some links:
Wikipedia about the VIC-IIFPGA64, A realtime Commodore 64 emulator in a FPGAChristian Bauer's article about the 6567/6569Rob Finch's FAL6567;---
Ok, now my assumptions about the VHDL:
clk is the main clock, running at ca. 32MHz (not exactly 32MHz, the value depends on PAL or NTSC and we'll take care about this later).
enaPixel has to be active every fourth clk cycle for having the equivalent of that ca. 8MHz pixel clock.
enaData is supposed to be active once within 16 clk cycles (once during phi=0 and once during phi=1).
baSync always is supposed to be 0.
di (8 Bit) is the input from the data bus.
diColor (4 Bit) is the input from the color RAM.
colorIndex (4 Bit) is supposed to be the output for every pixel displayed.
;---
Sorry for the low quality of the pictures... and for the odd notation.
Feel free to add some text (or better some drawings) when spotting any mistakes in my pictures,
I'm sure that there still might be quite a few in there.
;---
Edit: next thread:
TTL VIC-II, some ideas
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