Hello everyone. This is my first post and I want to briefly than you all who have contributed to the wealth of info at 6502.org.

I'm doing my own FPGA implementation of the 6502, and am confused as to how exactly the instruction fetch, decode, execution can overlap.

For example in an "AND a" operation the result would be stored in the accumulator at T4 (or T5?). However by that point the Timing Generation Logic has already been reset to T0 after T3 for fetching and decoding the next instruction. Is there some additional input to the Decode ROM (ref. Donald Hanson's diagram) that would allow the continued execution of "AND a" while the new instruction reaches the Instruction Reg?

I'd appreciate any pointers or reference to documentation.

I'm not sure exactly how the timing works on this, but it is easiest to consider the T0 state as the last state of the previous instruction. This state needs to fetch the new instruction into the instruction register, but is also free to finish off the current instruction. So, for example, while it is using the bus to read the next instruction it could also be updating an internal register.

So for the AND instruction you mention, it would go something like this (I've simplified a bit as the two phase clock adds a lot of complexity):

T1 Read the opcode (last cycle of previous instruction)
T2 Read address low into Input Data Latch (low)
T3 Read address high into Input Data Latch (high)
T4 Read value into ALU input register B, set up the ALU for AND, move A register to ALU input register A
T1 fetch next instruction, move ALU result (ADD) into A register

There are two registers that hold the instruction (partially decoded), the Pre-decode Register and the Instruction Register. Pre-decode is latched on Phi2 while Instruction Register is latched on Phi1. This is probably what allows the use of the current instruction while the next instruction is loaded into the CPU, The instruction register can be driving the state machine while the Pre-decode register is simultaneously being written to.

I don't think that all this is documented anywhere so you need to figure it out from the diagram and possibly look at Visual6502 to test your assumptions. With enough patience you could analyse what is happening in Visual6502 to understand this, but I think starting with the diagram is easier.

Hope that helps.

I'd agree with the suggestion to use visual6502 to investigate the machine's workings.

I think an important point is that that machine's control state is not limited to the bits of the T state flops. There are more than a handful of bits of state embedded in the "random control logic" section. It may be that what the datapath is going to do is informed by these bits, which were in turn previously loaded from the decode logic. There's a pipeline of control state which starts at the IR and moves towards the datapath.

Another possible source of insight is other existing HDL models of the CPU - Arlet's version is particularly small and simple, and follows the same organisation as the 6502 itself. Instead of looking at the details of individual instructions, look at the flow of control state.

jds and BigEd, thanks for the explanations, it's clearer now.

Since the IR is not updated until T1, then T0 for the next instruction could be thought of as the end of the current instruction. The current instruction plus state T0 would be decoded as the completion of the current instruction and a fetch of the next one.

Just a note on jds' AND timing description above, the Input Data Latch is actually 8 bits.