Welcome! I'll see if I can explain the way I understand it. Visual6502 is a switch-level simulation, so it models all the FETs (MOSFETs) as switches, either on or off. Except, as you note, it has special handing for the pullups.
In the 6502 the pullups are depletion mode, which means they are always on, but they are more weakly on when they are pulling up a very low voltage. This makes them more efficient than a pullup resistor: when the output of a logic gate is supposed to be low, they don't waste quite so much power. But for the purposes of visual6502, that's a detail which isn't part of the simulation.
So, most of the 6502 is made of logic gates, and in NMOS technology logic gates are built with pulldown networks where the logic happens, and a single pullup. If the logic network pulls down, one way or another, then the output is low. If the logic network doesn't pull down, then the pullup takes over and brings the output to a high level. The logic network can be modelled as a number of switches, which either conduct or don't - they are either closed or open - and the visual6502 simulator just has to figure out if there's a path to ground, or not.
Every node gets evaluated, potentially many times in each clock phase. If there's a path to ground, then the node is set to low. If there's no path to ground, the simulator needs to know if there's a pullup or not. If there is a pullup on this node, then the node is set to high. If there isn't, the node keeps its previous value.
It's important that a node can keep the previous value, as that's one of the ways that bits are stored on-chip.
In other words, visual6502 models pullups, and it doesn't really model them as one sort or another sort of transistor - it would be just the same code if the pullups were resistors.
(There's another evaluation visual6502 has to do, when a transistor turns on and connects two nodes, in the case that neither of them is pulled down or pulled up.)
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