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| [151] Dual Processor SBC http://forum.6502.org/viewtopic.php?f=7&t=406 |
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| Author: | p_mendham [ Mon Feb 25, 2002 1:48 pm ] |
| Post subject: | [151.1] Dual Processor SBC |
I'd quite like to knock together a dual processor 6502 SBC. Nothing fancy, a coupla 6522s a coupla serial ports, maybe some flash and some RAM. My only small issue is the bus sharing. I know that the 6502 only uses alternate bus cycles, and I seem to remember reading somewhere that on the cycle it doesn't use the data bus gets tristated but the address bu doesn't. Can I then just bolt on tristate drivers onto each of the processors and get them to turn on on alternate clock cycles? Obviously I'll have to stick tristate drivers onto the control bus lines aswell, won't I? I'm sure someone has done this before (or at least used the spare cycle for vid mem access or something), can anyone point me to a relevant web page? Thanks in advance Peter |
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| Author: | saipan59 [ Mon Feb 25, 2002 2:12 pm ] |
| Post subject: | [151.2] Dual Processor SBC |
I think your statements in .1 are all correct (Garth may need to correct me...). You may get some hints by looking at the schematics for something like a VIC-20 - the "VIC chip" shares RAM with the 6502 in a way similar to what you describe. One cool feature of the original 6800 CPU was that it has 3-state address lines - I have a plan to make a plan to make dual-CPU S-100 board with 6800's. Instead of alternate-cycle stuff, I plan to halt one CPU while the other is using the bus (I don't know what the "point" will be, it just seems like a cool thing to do!). In theory, no additional buffer chips are needed at all - just some logic to decide which CPU currently is halted. Pete |
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| Author: | GARTHWILSON [ Tue Feb 26, 2002 2:26 am ] |
| Post subject: | [151.3] Dual Processor SBC |
It sounds like you'll be spending some extra time in the timing diagrams. It might be profitable to see how the Apple II did the video, as I understand the processor and the video used opposite phases of the clock so they could both access the same memory at the same time at full speed without interference. If you don't have the diagrams, I or any of several others on the forum could probably send them to you. I'd have to photocopy and mail them since I don't have a scanner. Maybe someone else knows if they're on the web. I've toyed with the dual-processor idea a bit in past years, but never built such a system. If you've done it with other processors, maybe you could give us a discussion of the benefits and a few ins and outs. The idea has obvious merit, but I don't know how you would distribute the processing load beneficially without spending half the time on task management (defeating the purpose) or having one processor wait for the other to finish something so it has what it needs to in order to proceed. There was an article in The Computer Journal a few years back on multiprocessing. As I remember, it said the simplest way was to have the two (or more) processors rather loosely coupled. Each processor would have its own private memory filling much of its memory map, but a small part of its memory map would be for memory that is common to the other processor(s). This memory is then used as a mailbox to pass requests or instructions and data from one processor to the other. If you used dual-port RAM, I suppose the two processors would not even need to run at the same speed. Keep us posted on your evolving thoughts on this, and any progress in making such a system. |
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| Author: | saipan59 [ Thu Feb 28, 2002 12:01 pm ] |
| Post subject: | [151.4] Dual Processor SBC |
To elaborate a little on what I said in .2: In the VIC-20, and probably lots of similar machines, the video chip is really a CPU of sorts, and it generates the timing used by the real CPU. On alternate half-cycles, the VIC chip and the 6502 access the same RAM (namely the video memory). Tri-state buffers are used to keep them from clashing on the bus. The CPU runs at 1 Mhz, but they used a 6502A (2 Mhz chip), presumably to provide enough timing margin while the bus is being switched, etc. Meanwhile, despite what I said in .2, it occurs to me that dual-6800's could easily do the alternate-cycle approach, too: the 6800 has a "Tri-State Enable" pin, which can (I think) be used to tri-state the buses *without* halting the CPU. So, it would be simple to have the 2 CPUs alternately using the memory, without any extra 3-state buffers. BUT, as Garth said/hinted, it's hard to imagine the real benefit of going dual-CPU with either a 6502 or 6800. You could get the same "work done" with a single modern CPU that is running much faster. BUT, I may fool around with a dual-6800 design anyway, just because I like playing with vintage stuff. I have a bunch of old S-100 hardware, so I'm thinking of making a "switches and lights" control panel to plug into an S-100 backplane, then build the dual-6800 CPU (running at only 1 Mhz, of course!)... The S-100 bus is a trip - it was designed for the 8080. Pete |
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