I've been trying to emulate the 6502 in hardware.

The aim was to be able to plug the emulation hardware into a VIC20 or Commodore64 and run as if it were a real 6502.

I was trying to use a very fast embedded CPU to emulate the 6502. But realized this morning that to really emulate the 6502 at 1MHz, I would need something much faster than 100MHz.

Ben

I'm curious - what aspect of your plan would require something running at 100 Mhz or more?

I woulda thunk that a 20-30 Mhz CPU, with a little peripheral hardware, would do the job...

Pete

Okay, assuming a 50MHz cpu running at 50MIPS emulating a 6502.

For a 1000ns 6502 cycle time, you can have 50 cpu instructions. Within that, you have to output the address lines, output the r/w, sync, read in the data or output data and decode the opcode (if opcode read). Not forgetting that you need to sync with the external 6502 clock. 50 lines is just two pages in an editor. I wrote a function to go through a complete bus access cycle and came up to more than 60 instructions!

Email me at bluesky6@ix.netcom.com if you want to discuss some more.

If you use an SX from UBICOM (formerly SCENIX) I think you can do it. However, I'm not sure there's a 6502 in the VIC. Wasn't that a 6510?

In any case, it's necessary to study out the operation of the old 6502 at the level of the step-by-step listing of the items that appear at the device pins in the old MOS Technology hardware manual and emulate that.

It's achievable, I believe.

Uli

It's not quite that complicated, though it's not entirely simple either. If you take each opcode and program a short routine to execute it, you'll have a number of routines, fewer than 10-15 instructions long, I'd guess, that will do what the 6502 does with each opcode. Now, there are things in the area of address/status arithmetic that also have to be done, and they have to happen in the right sequence to make the correct things happen on the pins. Your opcode fetch cycle, however, is where the "trick" occurs, in that you simply do the equivalent of an indexed indirect jump through a table. That will route you to the routine that executes whatever is associated with that opcode byte. For an SX, each of those operations takes very little time. If there are 15 instructions, even at 50 MHz, that's only 300 ns.

Uli

The Commodore 64 and later Commodore computers (Plus/4, 128, 128D) had the 6510 processor or similar processors with an on-chip I/O port. The VIC-20, PETs, and other early Commodore computers used an NMOS 6502.

_________________
- Mike Naberezny (mike@naberezny.com) http://6502.org

I think you're taking the wrong approach.

You just need some hardware to map the 6502's address space
into a fast processor's address space and have the hardware
generate the proper 6502 read/write cycles.

The clock counts of most 6502 instructions are equal
to the number of memory accesses involved, with a few exceptions
(nop is two clocks, indexed read has a spurious read, etc).

With this kind of implementation, you basically have about half
a 6502 clock to actually emulate the instruction, or about 450 nsec.
I'm guessing you'd need about 10-15 instructions to emulate a 6502
instruction (maybe 5-7 instructions to do an indexed jump, and another 5-7 to actually emulate the instruction), so you'd probably need a RISC processor of about 20-30 Mhz to emulate a 1 Mhz 6502.

Toshi