Hi,

I've been gathering information to write a 100% perfect emulation of a machine that used a 6502 with some interesting timing issues on memory writes and reads depending when exactly they happen. So I've been trying to figure out exactly when they happen. I have a working scheme, but for one thing - instructions that modify a memory location via the absolute,y addressing mode. These take seven cycles, so I have assumed the following cycle breakdown is correct (assumes no carry on the low order addition) :

1) read instruction
2) read address low byte
3) add low byte and register, read high byte
4) read value
5) modify value
6) re-read high address byte
7) write

I have assumed that the temporary workspace used for modifying the value is the same spot that the address high byte would ordinarily be stored, because it is the only way I can see that would make seven cycles, and makes sense as a small CPU optimisation.

However, my problem is that all documentation (that says anything at all) says 'add 1 cycle if absolute indexed crosses a page boundary'. I would imagine that if a page boundary is crossed - in other words if step 3 causes carry, then this would mean a cycle was spent between my steps 3 and 4 incrementing the top byte. Hence one extra cycle. Which explains the comment for things such as lda abs,y, but when writing the value back, under my scheme the increment also has to occur between steps 6 and 7, causing a two cycle penalty.

So do I have to rethink my cycle breakdown, or have the documentation writers just forgotten to mention that the 1 cycle penalty is a 1 cycle penalty per address access within the instruction?

I apologise if this message appears more than once - I keep clicking 'post' only for the browser to sit around for about 5 minutes and report that the site has timed out or been reset. I hope I'm not sending one copy per click!

-Thomas

On an absolute,y addressing mode, the 6502 has a hardware "feature" where it reads absolute, then reads absolute,y.
If you read Leslie Ayling's article on his Flash card for the Apple II, it's mentioned in it.

Toshi

If you want to write a "correct" emulator for the NMOS 6502 as built by MOS Technology, the place to get the precise timing details is the MOS Technology Hardware Manual, which contains all the precise, cycle-by-cycle details about what appears on which pins at which point in the execution cycle of each instruction.

It tells you, for example, that when you execute an indexed write to <location + index> the processor READs from <location> before writing to <location + index>. If I hadn't known this twenty years ago, I wouldn't have been able to get a 1 MHz processor to synchronize with DRQ on a WD1793 transferring data at "double density."

There are lots of details that make up the basic operation of the 6502 hardware. They're described quite well in the Hardware Manual. That't the place to look.

Uli